* Re: [PATCH net-next 4/7] net: lan966x: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMP
From: Horatiu Vultur @ 2022-01-28 13:20 UTC (permalink / raw)
To: Richard Cochran
Cc: netdev, devicetree, linux-kernel, davem, kuba, robh+dt,
UNGLinuxDriver, linux, f.fainelli, vivien.didelot,
vladimir.oltean, andrew
In-Reply-To: <20220127215508.GA26514@hoboy.vegasvil.org>
The 01/27/2022 13:55, Richard Cochran wrote:
>
> On Thu, Jan 27, 2022 at 11:23:30AM +0100, Horatiu Vultur wrote:
>
> > diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c b/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
> > index 69d8f43e2b1b..9ff4d3fca5a1 100644
> > --- a/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
> > +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
> > @@ -35,6 +35,90 @@ static u64 lan966x_ptp_get_nominal_value(void)
> > return res;
> > }
> >
> > +int lan966x_ptp_hwtstamp_set(struct lan966x_port *port, struct ifreq *ifr)
> > +{
> > + struct lan966x *lan966x = port->lan966x;
> > + bool l2 = false, l4 = false;
> > + struct hwtstamp_config cfg;
> > + struct lan966x_phc *phc;
> > +
> > + /* For now don't allow to run ptp on ports that are part of a bridge,
> > + * because in case of transparent clock the HW will still forward the
> > + * frames, so there would be duplicate frames
> > + */
> > + if (lan966x->bridge_mask & BIT(port->chip_port))
> > + return -EINVAL;
> > +
> > + if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
> > + return -EFAULT;
> > +
> > + switch (cfg.tx_type) {
> > + case HWTSTAMP_TX_ON:
> > + port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
> > + break;
> > + case HWTSTAMP_TX_ONESTEP_SYNC:
> > + port->ptp_cmd = IFH_REW_OP_ONE_STEP_PTP;
> > + break;
> > + case HWTSTAMP_TX_OFF:
> > + port->ptp_cmd = IFH_REW_OP_NOOP;
> > + break;
> > + default:
> > + return -ERANGE;
> > + }
> > +
> > + mutex_lock(&lan966x->ptp_lock);
>
> No need to lock stack variables. Move locking down to ...
Good catch, will do that.
>
> > + switch (cfg.rx_filter) {
> > + case HWTSTAMP_FILTER_NONE:
> > + break;
> > + case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
> > + case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
> > + case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
> > + l4 = true;
> > + break;
> > + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
> > + case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
> > + case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
> > + l2 = true;
> > + break;
> > + case HWTSTAMP_FILTER_PTP_V2_EVENT:
> > + case HWTSTAMP_FILTER_PTP_V2_SYNC:
> > + case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
> > + l2 = true;
> > + l4 = true;
> > + break;
> > + default:
> > + mutex_unlock(&lan966x->ptp_lock);
> > + return -ERANGE;
> > + }
> > +
> > + if (l2 && l4)
> > + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
> > + else if (l2)
> > + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
> > + else if (l4)
> > + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
> > + else
> > + cfg.rx_filter = HWTSTAMP_FILTER_NONE;
> > +
> > + /* Commit back the result & save it */
>
> ... here
>
> > + phc = &lan966x->phc[LAN966X_PHC_PORT];
> > + memcpy(&phc->hwtstamp_config, &cfg, sizeof(cfg));
> > + mutex_unlock(&lan966x->ptp_lock);
> > +
> > + return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
> > +}
>
> Thanks,
> Richard
--
/Horatiu
^ permalink raw reply
* Re: [PATCH v4 2/2] dt-bindings: timer: sifive, clint: Group interrupt tuples
From: Anup Patel @ 2022-01-28 13:17 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Palmer Dabbelt, Paul Walmsley,
Anup Patel, Rob Herring, linux-kernel@vger.kernel.org List, DTML,
linux-riscv, Rob Herring
In-Reply-To: <62bf4ee6613550c07a99d4bd226ab0d33acae4c4.1643360652.git.geert@linux-m68k.org>
On Fri, Jan 28, 2022 at 2:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> To improve human readability and enable automatic validation, the tuples
> in "interrupts-extended" properties should be grouped using angle
> brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> v4:
> - Add Reviewed-by (this time for real ;-),
>
> v3:
> - Add Reviewed-by,
>
> v2:
> - Split in two patches.
> ---
> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index fe4b73c3f269fc0f..e64f46339079fa3f 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -57,10 +57,10 @@ examples:
> - |
> timer@2000000 {
> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
> - interrupts-extended = <&cpu1intc 3 &cpu1intc 7
> - &cpu2intc 3 &cpu2intc 7
> - &cpu3intc 3 &cpu3intc 7
> - &cpu4intc 3 &cpu4intc 7>;
> + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
> + <&cpu2intc 3>, <&cpu2intc 7>,
> + <&cpu3intc 3>, <&cpu3intc 7>,
> + <&cpu4intc 3>, <&cpu4intc 7>;
> reg = <0x2000000 0x10000>;
> };
> ...
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply
* Re: [PATCH v21 3/4] PCI: microchip: Add host driver for Microchip PCIe controller
From: Bjorn Helgaas @ 2022-01-28 13:16 UTC (permalink / raw)
To: Marc Zyngier
Cc: daire.mcnamara, lorenzo.pieralisi, bhelgaas, robh, linux-pci,
robh+dt, devicetree, david.abdurachmanov, cyril.jean
In-Reply-To: <87pmoc5gnb.wl-maz@kernel.org>
On Fri, Jan 28, 2022 at 09:55:04AM +0000, Marc Zyngier wrote:
> On Thu, 27 Jan 2022 20:20:00 +0000,
> Bjorn Helgaas <helgaas@kernel.org> wrote:
> > On Mon, Jan 25, 2021 at 04:29:33PM +0000, daire.mcnamara@microchip.com wrote:
> > > From: Daire McNamara <daire.mcnamara@microchip.com>
> > >
> > > Add support for the Microchip PolarFire PCIe controller when
> > > configured in host (Root Complex) mode.
> >
> > > +static void mc_handle_msi(struct irq_desc *desc)
> > > +{
> > > + struct mc_port *port = irq_desc_get_handler_data(desc);
> > > + struct device *dev = port->dev;
> > > + struct mc_msi *msi = &port->msi;
> > > + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> > > + unsigned long status;
> > > + u32 bit;
> > > + u32 virq;
> > > +
> > > + status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
> > > + if (status & PM_MSI_INT_MSI_MASK) {
> > > + status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
> > > + for_each_set_bit(bit, &status, msi->num_vectors) {
> > > + virq = irq_find_mapping(msi->dev_domain, bit);
> > > + if (virq)
> > > + generic_handle_irq(virq);
>
> Wrong construct. Please use generic_handle_domain_irq().
I responded to this old posting because it was the most recent one
that included the code below. This irq_find_mapping() bit has since
been updated:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-microchip-host.c?id=v5.17-rc1#n406
> > > + else
> > > + dev_err_ratelimited(dev, "bad MSI IRQ %d\n", bit);
> > > + }
> > > + }
> > > +}
> > > +
> > > +static void mc_msi_bottom_irq_ack(struct irq_data *data)
> > > +{
> > > + struct mc_port *port = irq_data_get_irq_chip_data(data);
> > > + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> > > + u32 bitpos = data->hwirq;
> > > + unsigned long status;
> > > +
> > > + writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
> > > + status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
> > > + if (!status)
> > > + writel_relaxed(BIT(PM_MSI_INT_MSI_SHIFT), bridge_base_addr + ISTATUS_LOCAL);
> >
> > This looks like it might be racy. What happens if we read 0 from
> > ISTATUS_MSI, but a new MSI is latched before we write ISTATUS_LOCAL?
>
> I agree, this looks really odd. The irq_ack callback is per interrupt,
> while this seems to deal with some global state. This cannot be right.
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: timer: sifive, clint: Fix number of interrupts
From: Anup Patel @ 2022-01-28 13:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Palmer Dabbelt, Paul Walmsley,
Anup Patel, Rob Herring, linux-kernel@vger.kernel.org List, DTML,
linux-riscv, Rob Herring
In-Reply-To: <e6a4c5b20d2acb52125d7d6e6c7e3694d7cb182c.1643360652.git.geert@linux-m68k.org>
On Fri, Jan 28, 2022 at 2:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> The number of interrupts lacks an upper bound, thus assuming one,
> causing properly grouped "interrupts-extended" properties to be flagged
> as an error by "make dtbs_check".
>
> Fix this by adding the missing "maxItems", using the architectural
> maximum of 4095 interrupts.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Acked-by: Rob Herring <robh@kernel.org>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> v4:
> - Use architectural maximum instead of practical maximum of 10,
>
> v3:
> - Add Acked-by,
>
> v2:
> - Split in two patches,
> - Improve patch description and document limit rationale.
> ---
> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index 8d5f4687add9e81e..fe4b73c3f269fc0f 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -44,6 +44,7 @@ properties:
>
> interrupts-extended:
> minItems: 1
> + maxItems: 4095
>
> additionalProperties: false
>
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply
* Re: [PATCH net-next 2/7] net: lan966x: Add registers that are use for ptp functionality
From: Horatiu Vultur @ 2022-01-28 13:15 UTC (permalink / raw)
To: Richard Cochran
Cc: netdev, devicetree, linux-kernel, davem, kuba, robh+dt,
UNGLinuxDriver, linux, f.fainelli, vivien.didelot,
vladimir.oltean, andrew
In-Reply-To: <20220127151836.GA20642@hoboy.vegasvil.org>
The 01/27/2022 07:18, Richard Cochran wrote:
Hi Richard,
>
> On Thu, Jan 27, 2022 at 11:23:28AM +0100, Horatiu Vultur wrote:
> > This patch adds the registers that will be used to configure the PHC in
> > the HW.
>
> See "This patch" in Documentation/process/submitting-patches.rst
Yes, I will update this in the next version.
>
> Thanks,
> Richard
--
/Horatiu
^ permalink raw reply
* Re: [PATCH] ASoC: dt-bindings: Centralize the 'sound-dai' definition
From: Mark Brown @ 2022-01-28 13:06 UTC (permalink / raw)
To: Rob Herring
Cc: Jerome Brunet, Liam Girdwood, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Sylwester Nawrocki, Rohit kumar, Cheng-Yi Chiang, Shengjiu Wang,
Srinivas Kandagatla, Jonathan Bakker, Krzysztof Kozlowski,
alsa-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-msm
In-Reply-To: <20220126231427.1638089-1-robh@kernel.org>
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On Wed, Jan 26, 2022 at 05:14:27PM -0600, Rob Herring wrote:
> 'sound-dai' is a common property, but has duplicate type definitions.
> Create a new common definition to define the type and then update all
> the other occurrences to just define how many entries there are just
> like other phandle+arg properties.
Acked-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: display: imx: Add fsl,imx21-lcdc docs
From: Rob Herring @ 2022-01-28 13:04 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, dri-devel,
linux-arm-kernel, devicetree
In-Reply-To: <20220128105849.368438-2-u.kleine-koenig@pengutronix.de>
On Fri, Jan 28, 2022 at 4:59 AM Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> From: Marian Cichy <m.cichy@pengutronix.de>
>
> This files documents the device tree for the new imx21-lcdc DRM driver.
No, bindings document h/w and the h/w has not changed. We already have
a binding for the LCDC.
>
> Signed-off-by: Marian Cichy <m.cichy@pengutronix.de>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> .../bindings/display/imx/fsl,imx21-lcdc.yaml | 79 +++++++++++++++++++
> 1 file changed, 79 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx21-lcdc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx21-lcdc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx21-lcdc.yaml
> new file mode 100644
> index 000000000000..edf71cfac81c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx21-lcdc.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx21-lcdc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX21 LCD Controller
> +
> +maintainers:
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: fsl,imx21-lcdc
> + - items:
> + - enum:
> + - fsl,imx25-lcdc
> + - fsl,imx27-lcdc
> + - const: fsl,imx21-lcdc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: ipg
> + - const: per
> + - const: ahb
> +
> + resets:
> + maxItems: 1
> +
> + port:
> + type: object
> + description:
> + "Video port for DPI RGB output."
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - port
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + lcdc: lcdc@53fbc000 {
> + compatible = "fsl,imx25-lcdc", "fsl,imx21-lcdc";
> + reg = <0x53fbc000 0x4000>;
> + interrupts = <39>;
> + clocks = <&clks 103>, <&clks 66>, <&clks 49>;
> + clock-names = "ipg", "ahb", "per";
> +
> + port {
> + parallel_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> +
> + };
> +
> + panel: panel {
> + compatible = "edt,etm0700g0dh6";
> + power-supply = <&lcd_supply>;
> + backlight = <&bl>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <¶llel_out>;
> + };
> + };
> + };
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH -next] dt-bindings:spi: Fix error for test.
From: Mark Brown @ 2022-01-28 12:57 UTC (permalink / raw)
To: Li-hao Kuo; +Cc: robh+dt, linux-spi, devicetree, linux-kernel, wells.lu, lh.kuo
In-Reply-To: <1643337290-1376-1-git-send-email-lhjeff911@gmail.com>
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On Fri, Jan 28, 2022 at 10:34:50AM +0800, Li-hao Kuo wrote:
> Fix error for test remove the include path and modify parameters
> ---
> Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
You've not provided a Signed-off-by for this so I can't do anything with
it, please see Documentation/process/submitting-patches.rst for details
on what this is and why it's important.
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^ permalink raw reply
* Re: [PATCH -next] spi: Fix compiler warning for kernel test
From: Mark Brown @ 2022-01-28 12:57 UTC (permalink / raw)
To: Li-hao Kuo; +Cc: sfr, linux-spi, devicetree, linux-kernel, wells.lu, lh.kuo
In-Reply-To: <1643336485-10942-1-git-send-email-lhjeff911@gmail.com>
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On Fri, Jan 28, 2022 at 10:21:25AM +0800, Li-hao Kuo wrote:
> ---
> drivers/spi/spi-sunplus-sp7021.c | 10 ++++++----
You've not provided a Signed-off-by for this so I can't do anything with
it, please see Documentation/process/submitting-patches.rst for details
on what this is and why it's important.
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^ permalink raw reply
* Re: [PATCH v10 02/13] iommu/mediatek-v1: Free the existed fwspec if the master dev already has
From: Mauro Carvalho Chehab @ 2022-01-28 12:45 UTC (permalink / raw)
To: Yong Wu, Matthias Brugger
Cc: Hans Verkuil, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
David Airlie, Evan Green, Robin Murphy, Tomasz Figa, Will Deacon,
linux-mediatek, srv_heupstream, devicetree, linux-kernel,
linux-arm-kernel, iommu, youlin.pei, Matthias Kaehlcke, anan.sun,
yi.kuo, acourbot, linux-media, dri-devel, Daniel Vetter,
Chun-Kuang Hu, Philipp Zabel, Tiffany Lin, Dafna Hirschfeld,
Hsin-Yi Wang, Eizan Miyamoto, anthony.huang, Frank Wunderlich,
mingyuan.ma, yf.wang, libo.kang, AngeloGioacchino Del Regno
In-Reply-To: <20220128134055.720bb43c@coco.lan>
Em Fri, 28 Jan 2022 13:40:55 +0100
Mauro Carvalho Chehab <mchehab@kernel.org> escreveu:
> Hi Matthias/Yong,
>
> Are you ok if this patch gets merged via the media tree together with the
> remaining series, or do you prefer to apply it via SoC tree instead?
Same questions for other patches touching files outside drivers/media
on this pull request:
https://patchwork.kernel.org/project/linux-mediatek/patch/7af52d61-47c7-581d-62ed-76a7f8315b16@xs4all.nl/
Like those:
0004-0013-iommu-mediatek-v1-Free-the-existed-fwspec-if-the-mas.patch
0005-0013-iommu-mediatek-Return-ENODEV-if-the-device-is-NULL.patch
0006-0013-iommu-mediatek-Add-probe_defer-for-smi-larb.patch
0007-0013-iommu-mediatek-Add-device_link-between-the-consumer-.patch
Regards,
Mauro
>
> Regards,
> Mauro
>
>
> Em Mon, 17 Jan 2022 15:04:59 +0800
> Yong Wu <yong.wu@mediatek.com> escreveu:
>
> > When the iommu master device enters of_iommu_xlate, the ops may be
> > NULL(iommu dev is defered), then it will initialize the fwspec here:
> >
> > [<c0c9c5bc>] (dev_iommu_fwspec_set) from [<c06bda80>]
> > (iommu_fwspec_init+0xbc/0xd4)
> > [<c06bd9c4>] (iommu_fwspec_init) from [<c06c0db4>]
> > (of_iommu_xlate+0x7c/0x12c)
> > [<c06c0d38>] (of_iommu_xlate) from [<c06c10e8>]
> > (of_iommu_configure+0x144/0x1e8)
> >
> > BUT the mtk_iommu_v1.c only supports arm32, the probing flow still is a bit
> > weird. We always expect create the fwspec internally. otherwise it will
> > enter here and return fail.
> >
> > static int mtk_iommu_create_mapping(struct device *dev,
> > struct of_phandle_args *args)
> > {
> > ...
> > if (!fwspec) {
> > ....
> > } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
> > >>>>>>>>>>Enter here. return fail.<<<<<<<<<<<<
> > return -EINVAL;
> > }
> > ...
> > }
> >
> > Thus, Free the existed fwspec if the master device already has fwspec.
> >
> > This issue is reported at:
> > https://lore.kernel.org/linux-mediatek/trinity-7d9ebdc9-4849-4d93-bfb5-429dcb4ee449-1626253158870@3c-app-gmx-bs01/
> >
> > Reported-by: Frank Wunderlich <frank-w@public-files.de>
> > Tested-by: Frank Wunderlich <frank-w@public-files.de> # BPI-R2/MT7623
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Acked-by: Joerg Roedel <jroedel@suse.de>
> > Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/iommu/mtk_iommu_v1.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> > index be22fcf988ce..1467ba1e4417 100644
> > --- a/drivers/iommu/mtk_iommu_v1.c
> > +++ b/drivers/iommu/mtk_iommu_v1.c
> > @@ -425,6 +425,15 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
> > struct mtk_iommu_data *data;
> > int err, idx = 0;
> >
> > + /*
> > + * In the deferred case, free the existed fwspec.
> > + * Always initialize the fwspec internally.
> > + */
> > + if (fwspec) {
> > + iommu_fwspec_free(dev);
> > + fwspec = dev_iommu_fwspec_get(dev);
> > + }
> > +
> > while (!of_parse_phandle_with_args(dev->of_node, "iommus",
> > "#iommu-cells",
> > idx, &iommu_spec)) {
>
>
>
> Thanks,
> Mauro
Thanks,
Mauro
^ permalink raw reply
* Re: [PATCH v10 02/13] iommu/mediatek-v1: Free the existed fwspec if the master dev already has
From: Mauro Carvalho Chehab @ 2022-01-28 12:40 UTC (permalink / raw)
To: Yong Wu, Matthias Brugger
Cc: Hans Verkuil, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
David Airlie, Evan Green, Robin Murphy, Tomasz Figa, Will Deacon,
linux-mediatek, srv_heupstream, devicetree, linux-kernel,
linux-arm-kernel, iommu, youlin.pei, Matthias Kaehlcke, anan.sun,
yi.kuo, acourbot, linux-media, dri-devel, Daniel Vetter,
Chun-Kuang Hu, Philipp Zabel, Tiffany Lin, Dafna Hirschfeld,
Hsin-Yi Wang, Eizan Miyamoto, anthony.huang, Frank Wunderlich,
mingyuan.ma, yf.wang, libo.kang, AngeloGioacchino Del Regno
In-Reply-To: <20220117070510.17642-3-yong.wu@mediatek.com>
Hi Matthias/Yong,
Are you ok if this patch gets merged via the media tree together with the
remaining series, or do you prefer to apply it via SoC tree instead?
Regards,
Mauro
Em Mon, 17 Jan 2022 15:04:59 +0800
Yong Wu <yong.wu@mediatek.com> escreveu:
> When the iommu master device enters of_iommu_xlate, the ops may be
> NULL(iommu dev is defered), then it will initialize the fwspec here:
>
> [<c0c9c5bc>] (dev_iommu_fwspec_set) from [<c06bda80>]
> (iommu_fwspec_init+0xbc/0xd4)
> [<c06bd9c4>] (iommu_fwspec_init) from [<c06c0db4>]
> (of_iommu_xlate+0x7c/0x12c)
> [<c06c0d38>] (of_iommu_xlate) from [<c06c10e8>]
> (of_iommu_configure+0x144/0x1e8)
>
> BUT the mtk_iommu_v1.c only supports arm32, the probing flow still is a bit
> weird. We always expect create the fwspec internally. otherwise it will
> enter here and return fail.
>
> static int mtk_iommu_create_mapping(struct device *dev,
> struct of_phandle_args *args)
> {
> ...
> if (!fwspec) {
> ....
> } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
> >>>>>>>>>>Enter here. return fail.<<<<<<<<<<<<
> return -EINVAL;
> }
> ...
> }
>
> Thus, Free the existed fwspec if the master device already has fwspec.
>
> This issue is reported at:
> https://lore.kernel.org/linux-mediatek/trinity-7d9ebdc9-4849-4d93-bfb5-429dcb4ee449-1626253158870@3c-app-gmx-bs01/
>
> Reported-by: Frank Wunderlich <frank-w@public-files.de>
> Tested-by: Frank Wunderlich <frank-w@public-files.de> # BPI-R2/MT7623
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Acked-by: Joerg Roedel <jroedel@suse.de>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/iommu/mtk_iommu_v1.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> index be22fcf988ce..1467ba1e4417 100644
> --- a/drivers/iommu/mtk_iommu_v1.c
> +++ b/drivers/iommu/mtk_iommu_v1.c
> @@ -425,6 +425,15 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
> struct mtk_iommu_data *data;
> int err, idx = 0;
>
> + /*
> + * In the deferred case, free the existed fwspec.
> + * Always initialize the fwspec internally.
> + */
> + if (fwspec) {
> + iommu_fwspec_free(dev);
> + fwspec = dev_iommu_fwspec_get(dev);
> + }
> +
> while (!of_parse_phandle_with_args(dev->of_node, "iommus",
> "#iommu-cells",
> idx, &iommu_spec)) {
Thanks,
Mauro
^ permalink raw reply
* [PATCH v3 5/5] arm64: tegra: APE sound card for Jetson AGX Orin
From: Sameer Pujar @ 2022-01-28 12:37 UTC (permalink / raw)
To: broonie, lgirdwood, tiwai, perex, robh+dt, thierry.reding
Cc: jonathanh, mkumard, devicetree, linux-tegra, linux-kernel,
alsa-devel, Sameer Pujar
In-Reply-To: <1643373476-8538-1-git-send-email-spujar@nvidia.com>
Add audio-graph based sound card support on Jetson AGX Orin
platform. The sound card binds following modules:
* I/O interfaces such as I2S and DMIC (to be specific I2S1,
I2S2, I2S4, I2S6 and DMIC3 instances).
* HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all
the available instances).
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
.../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 1783 ++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 17 +
2 files changed, 1800 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index efbbb87..4ae0e9e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -13,6 +13,1734 @@
serial0 = &tcu;
};
+ bus@0 {
+ aconnect@2900000 {
+ status = "okay";
+
+ ahub@2900800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0_ep: endpoint {
+ remote-endpoint = <&admaif0_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1_ep: endpoint {
+ remote-endpoint = <&admaif1_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2_ep: endpoint {
+ remote-endpoint = <&admaif2_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3_ep: endpoint {
+ remote-endpoint = <&admaif3_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4_ep: endpoint {
+ remote-endpoint = <&admaif4_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5_ep: endpoint {
+ remote-endpoint = <&admaif5_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6_ep: endpoint {
+ remote-endpoint = <&admaif6_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7_ep: endpoint {
+ remote-endpoint = <&admaif7_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8_ep: endpoint {
+ remote-endpoint = <&admaif8_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9_ep: endpoint {
+ remote-endpoint = <&admaif9_ep>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10_ep: endpoint {
+ remote-endpoint = <&admaif10_ep>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11_ep: endpoint {
+ remote-endpoint = <&admaif11_ep>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12_ep: endpoint {
+ remote-endpoint = <&admaif12_ep>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13_ep: endpoint {
+ remote-endpoint = <&admaif13_ep>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14_ep: endpoint {
+ remote-endpoint = <&admaif14_ep>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15_ep: endpoint {
+ remote-endpoint = <&admaif15_ep>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16_ep: endpoint {
+ remote-endpoint = <&admaif16_ep>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17_ep: endpoint {
+ remote-endpoint = <&admaif17_ep>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18_ep: endpoint {
+ remote-endpoint = <&admaif18_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19_ep: endpoint {
+ remote-endpoint = <&admaif19_ep>;
+ };
+ };
+
+ xbar_i2s1_port: port@14 {
+ reg = <0x14>;
+
+ xbar_i2s1_ep: endpoint {
+ remote-endpoint = <&i2s1_cif_ep>;
+ };
+ };
+
+ xbar_i2s2_port: port@15 {
+ reg = <0x15>;
+
+ xbar_i2s2_ep: endpoint {
+ remote-endpoint = <&i2s2_cif_ep>;
+ };
+ };
+
+ xbar_i2s4_port: port@17 {
+ reg = <0x17>;
+
+ xbar_i2s4_ep: endpoint {
+ remote-endpoint = <&i2s4_cif_ep>;
+ };
+ };
+
+ xbar_i2s6_port: port@19 {
+ reg = <0x19>;
+
+ xbar_i2s6_ep: endpoint {
+ remote-endpoint = <&i2s6_cif_ep>;
+ };
+ };
+
+ xbar_dmic3_port: port@1c {
+ reg = <0x1c>;
+
+ xbar_dmic3_ep: endpoint {
+ remote-endpoint = <&dmic3_cif_ep>;
+ };
+ };
+
+ xbar_sfc1_in_port: port@20 {
+ reg = <0x20>;
+
+ xbar_sfc1_in_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_in_ep>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ xbar_sfc1_out_ep: endpoint {
+ remote-endpoint = <&sfc1_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@22 {
+ reg = <0x22>;
+
+ xbar_sfc2_in_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_in_ep>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ xbar_sfc2_out_ep: endpoint {
+ remote-endpoint = <&sfc2_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@24 {
+ reg = <0x24>;
+
+ xbar_sfc3_in_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_in_ep>;
+ };
+ };
+
+ port@25 {
+ reg = <0x25>;
+
+ xbar_sfc3_out_ep: endpoint {
+ remote-endpoint = <&sfc3_cif_out_ep>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@26 {
+ reg = <0x26>;
+
+ xbar_sfc4_in_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_in_ep>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_sfc4_out_ep: endpoint {
+ remote-endpoint = <&sfc4_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_mvc1_in_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_in_ep>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_mvc1_out_ep: endpoint {
+ remote-endpoint = <&mvc1_cif_out_ep>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@2a {
+ reg = <0x2a>;
+
+ xbar_mvc2_in_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_in_ep>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_mvc2_out_ep: endpoint {
+ remote-endpoint = <&mvc2_cif_out_ep>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@2c {
+ reg = <0x2c>;
+
+ xbar_amx1_in1_ep: endpoint {
+ remote-endpoint = <&amx1_in1_ep>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_amx1_in2_ep: endpoint {
+ remote-endpoint = <&amx1_in2_ep>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@2e {
+ reg = <0x2e>;
+
+ xbar_amx1_in3_ep: endpoint {
+ remote-endpoint = <&amx1_in3_ep>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@2f {
+ reg = <0x2f>;
+
+ xbar_amx1_in4_ep: endpoint {
+ remote-endpoint = <&amx1_in4_ep>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_amx1_out_ep: endpoint {
+ remote-endpoint = <&amx1_out_ep>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@31 {
+ reg = <0x31>;
+
+ xbar_amx2_in1_ep: endpoint {
+ remote-endpoint = <&amx2_in1_ep>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@32 {
+ reg = <0x32>;
+
+ xbar_amx2_in2_ep: endpoint {
+ remote-endpoint = <&amx2_in2_ep>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@33 {
+ reg = <0x33>;
+
+ xbar_amx2_in3_ep: endpoint {
+ remote-endpoint = <&amx2_in3_ep>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@34 {
+ reg = <0x34>;
+
+ xbar_amx2_in4_ep: endpoint {
+ remote-endpoint = <&amx2_in4_ep>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ xbar_amx2_out_ep: endpoint {
+ remote-endpoint = <&amx2_out_ep>;
+ };
+ };
+
+ xbar_amx3_in1_port: port@36 {
+ reg = <0x36>;
+
+ xbar_amx3_in1_ep: endpoint {
+ remote-endpoint = <&amx3_in1_ep>;
+ };
+ };
+
+ xbar_amx3_in2_port: port@37 {
+ reg = <0x37>;
+
+ xbar_amx3_in2_ep: endpoint {
+ remote-endpoint = <&amx3_in2_ep>;
+ };
+ };
+
+ xbar_amx3_in3_port: port@38 {
+ reg = <0x38>;
+
+ xbar_amx3_in3_ep: endpoint {
+ remote-endpoint = <&amx3_in3_ep>;
+ };
+ };
+
+ xbar_amx3_in4_port: port@39 {
+ reg = <0x39>;
+
+ xbar_amx3_in4_ep: endpoint {
+ remote-endpoint = <&amx3_in4_ep>;
+ };
+ };
+
+ port@3a {
+ reg = <0x3a>;
+
+ xbar_amx3_out_ep: endpoint {
+ remote-endpoint = <&amx3_out_ep>;
+ };
+ };
+
+ xbar_amx4_in1_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_amx4_in1_ep: endpoint {
+ remote-endpoint = <&amx4_in1_ep>;
+ };
+ };
+
+ xbar_amx4_in2_port: port@3c {
+ reg = <0x3c>;
+
+ xbar_amx4_in2_ep: endpoint {
+ remote-endpoint = <&amx4_in2_ep>;
+ };
+ };
+
+ xbar_amx4_in3_port: port@3d {
+ reg = <0x3d>;
+
+ xbar_amx4_in3_ep: endpoint {
+ remote-endpoint = <&amx4_in3_ep>;
+ };
+ };
+
+ xbar_amx4_in4_port: port@3e {
+ reg = <0x3e>;
+
+ xbar_amx4_in4_ep: endpoint {
+ remote-endpoint = <&amx4_in4_ep>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_amx4_out_ep: endpoint {
+ remote-endpoint = <&amx4_out_ep>;
+ };
+ };
+
+ xbar_adx1_in_port: port@40 {
+ reg = <0x40>;
+
+ xbar_adx1_in_ep: endpoint {
+ remote-endpoint = <&adx1_in_ep>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ xbar_adx1_out1_ep: endpoint {
+ remote-endpoint = <&adx1_out1_ep>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_adx1_out2_ep: endpoint {
+ remote-endpoint = <&adx1_out2_ep>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ xbar_adx1_out3_ep: endpoint {
+ remote-endpoint = <&adx1_out3_ep>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_adx1_out4_ep: endpoint {
+ remote-endpoint = <&adx1_out4_ep>;
+ };
+ };
+
+ xbar_adx2_in_port: port@45 {
+ reg = <0x45>;
+
+ xbar_adx2_in_ep: endpoint {
+ remote-endpoint = <&adx2_in_ep>;
+ };
+ };
+
+ port@46 {
+ reg = <0x46>;
+
+ xbar_adx2_out1_ep: endpoint {
+ remote-endpoint = <&adx2_out1_ep>;
+ };
+ };
+
+ port@47 {
+ reg = <0x47>;
+
+ xbar_adx2_out2_ep: endpoint {
+ remote-endpoint = <&adx2_out2_ep>;
+ };
+ };
+
+ port@48 {
+ reg = <0x48>;
+
+ xbar_adx2_out3_ep: endpoint {
+ remote-endpoint = <&adx2_out3_ep>;
+ };
+ };
+
+ port@49 {
+ reg = <0x49>;
+
+ xbar_adx2_out4_ep: endpoint {
+ remote-endpoint = <&adx2_out4_ep>;
+ };
+ };
+
+ xbar_adx3_in_port: port@4a {
+ reg = <0x4a>;
+
+ xbar_adx3_in_ep: endpoint {
+ remote-endpoint = <&adx3_in_ep>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ xbar_adx3_out1_ep: endpoint {
+ remote-endpoint = <&adx3_out1_ep>;
+ };
+ };
+
+ port@4c {
+ reg = <0x4c>;
+
+ xbar_adx3_out2_ep: endpoint {
+ remote-endpoint = <&adx3_out2_ep>;
+ };
+ };
+
+ port@4d {
+ reg = <0x4d>;
+
+ xbar_adx3_out3_ep: endpoint {
+ remote-endpoint = <&adx3_out3_ep>;
+ };
+ };
+
+ port@4e {
+ reg = <0x4e>;
+
+ xbar_adx3_out4_ep: endpoint {
+ remote-endpoint = <&adx3_out4_ep>;
+ };
+ };
+
+ xbar_adx4_in_port: port@4f {
+ reg = <0x4f>;
+
+ xbar_adx4_in_ep: endpoint {
+ remote-endpoint = <&adx4_in_ep>;
+ };
+ };
+
+ port@50 {
+ reg = <0x50>;
+
+ xbar_adx4_out1_ep: endpoint {
+ remote-endpoint = <&adx4_out1_ep>;
+ };
+ };
+
+ port@51 {
+ reg = <0x51>;
+
+ xbar_adx4_out2_ep: endpoint {
+ remote-endpoint = <&adx4_out2_ep>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ xbar_adx4_out3_ep: endpoint {
+ remote-endpoint = <&adx4_out3_ep>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ xbar_adx4_out4_ep: endpoint {
+ remote-endpoint = <&adx4_out4_ep>;
+ };
+ };
+
+ xbar_mixer_in1_port: port@54 {
+ reg = <0x54>;
+
+ xbar_mixer_in1_ep: endpoint {
+ remote-endpoint = <&mixer_in1_ep>;
+ };
+ };
+
+ xbar_mixer_in2_port: port@55 {
+ reg = <0x55>;
+
+ xbar_mixer_in2_ep: endpoint {
+ remote-endpoint = <&mixer_in2_ep>;
+ };
+ };
+
+ xbar_mixer_in3_port: port@56 {
+ reg = <0x56>;
+
+ xbar_mixer_in3_ep: endpoint {
+ remote-endpoint = <&mixer_in3_ep>;
+ };
+ };
+
+ xbar_mixer_in4_port: port@57 {
+ reg = <0x57>;
+
+ xbar_mixer_in4_ep: endpoint {
+ remote-endpoint = <&mixer_in4_ep>;
+ };
+ };
+
+ xbar_mixer_in5_port: port@58 {
+ reg = <0x58>;
+
+ xbar_mixer_in5_ep: endpoint {
+ remote-endpoint = <&mixer_in5_ep>;
+ };
+ };
+
+ xbar_mixer_in6_port: port@59 {
+ reg = <0x59>;
+
+ xbar_mixer_in6_ep: endpoint {
+ remote-endpoint = <&mixer_in6_ep>;
+ };
+ };
+
+ xbar_mixer_in7_port: port@5a {
+ reg = <0x5a>;
+
+ xbar_mixer_in7_ep: endpoint {
+ remote-endpoint = <&mixer_in7_ep>;
+ };
+ };
+
+ xbar_mixer_in8_port: port@5b {
+ reg = <0x5b>;
+
+ xbar_mixer_in8_ep: endpoint {
+ remote-endpoint = <&mixer_in8_ep>;
+ };
+ };
+
+ xbar_mixer_in9_port: port@5c {
+ reg = <0x5c>;
+
+ xbar_mixer_in9_ep: endpoint {
+ remote-endpoint = <&mixer_in9_ep>;
+ };
+ };
+
+ xbar_mixer_in10_port: port@5d {
+ reg = <0x5d>;
+
+ xbar_mixer_in10_ep: endpoint {
+ remote-endpoint = <&mixer_in10_ep>;
+ };
+ };
+
+ port@5e {
+ reg = <0x5e>;
+
+ xbar_mixer_out1_ep: endpoint {
+ remote-endpoint = <&mixer_out1_ep>;
+ };
+ };
+
+ port@5f {
+ reg = <0x5f>;
+
+ xbar_mixer_out2_ep: endpoint {
+ remote-endpoint = <&mixer_out2_ep>;
+ };
+ };
+
+ port@60 {
+ reg = <0x60>;
+
+ xbar_mixer_out3_ep: endpoint {
+ remote-endpoint = <&mixer_out3_ep>;
+ };
+ };
+
+ port@61 {
+ reg = <0x61>;
+
+ xbar_mixer_out4_ep: endpoint {
+ remote-endpoint = <&mixer_out4_ep>;
+ };
+ };
+
+ port@62 {
+ reg = <0x62>;
+
+ xbar_mixer_out5_ep: endpoint {
+ remote-endpoint = <&mixer_out5_ep>;
+ };
+ };
+ };
+
+ i2s@2901000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s1_ep>;
+ };
+ };
+
+ i2s1_port: port@1 {
+ reg = <1>;
+
+ i2s1_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s2_ep>;
+ };
+ };
+
+ i2s2_port: port@1 {
+ reg = <1>;
+
+ i2s2_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901300 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s4_ep>;
+ };
+ };
+
+ i2s4_port: port@1 {
+ reg = <1>;
+
+ i2s4_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901500 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s6_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s6_ep>;
+ };
+ };
+
+ i2s6_port: port@1 {
+ reg = <1>;
+
+ i2s6_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ sfc@2902000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_in_ep>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_in_ep>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_in_ep>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc3_out_ep>;
+ };
+ };
+ };
+ };
+
+ sfc@2902600 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_in_ep>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_sfc4_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@2903000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx1_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_in4_ep>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx1_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@2903100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx2_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx2_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx2_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx2_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_in4_ep>;
+ };
+ };
+
+ amx2_out_port: port@4 {
+ reg = <4>;
+
+ amx2_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx2_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@2903200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx3_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx3_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx3_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx3_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_in4_ep>;
+ };
+ };
+
+ amx3_out_port: port@4 {
+ reg = <4>;
+
+ amx3_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx3_out_ep>;
+ };
+ };
+ };
+ };
+
+ amx@2903300 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx4_in1_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx4_in2_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx4_in3_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx4_in4_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_in4_ep>;
+ };
+ };
+
+ amx4_out_port: port@4 {
+ reg = <4>;
+
+ amx4_out_ep: endpoint {
+ remote-endpoint = <&xbar_amx4_out_ep>;
+ };
+ };
+ };
+ };
+
+ adx@2903800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx1_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_in_ep>;
+ };
+ };
+
+ adx1_out1_port: port@1 {
+ reg = <1>;
+
+ adx1_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out1_ep>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out2_ep>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out3_ep>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx1_out4_ep>;
+ };
+ };
+ };
+ };
+
+ adx@2903900 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx2_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_in_ep>;
+ };
+ };
+
+ adx2_out1_port: port@1 {
+ reg = <1>;
+
+ adx2_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out1_ep>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out2_ep>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out3_ep>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx2_out4_ep>;
+ };
+ };
+ };
+ };
+
+ adx@2903a00 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx3_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_in_ep>;
+ };
+ };
+
+ adx3_out1_port: port@1 {
+ reg = <1>;
+
+ adx3_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out1_ep>;
+ };
+ };
+
+ adx3_out2_port: port@2 {
+ reg = <2>;
+
+ adx3_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out2_ep>;
+ };
+ };
+
+ adx3_out3_port: port@3 {
+ reg = <3>;
+
+ adx3_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out3_ep>;
+ };
+ };
+
+ adx3_out4_port: port@4 {
+ reg = <4>;
+
+ adx3_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx3_out4_ep>;
+ };
+ };
+ };
+ };
+
+ adx@2903b00 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx4_in_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_in_ep>;
+ };
+ };
+
+ adx4_out1_port: port@1 {
+ reg = <1>;
+
+ adx4_out1_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out1_ep>;
+ };
+ };
+
+ adx4_out2_port: port@2 {
+ reg = <2>;
+
+ adx4_out2_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out2_ep>;
+ };
+ };
+
+ adx4_out3_port: port@3 {
+ reg = <3>;
+
+ adx4_out3_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out3_ep>;
+ };
+ };
+
+ adx4_out4_port: port@4 {
+ reg = <4>;
+
+ adx4_out4_ep: endpoint {
+ remote-endpoint = <&xbar_adx4_out4_ep>;
+ };
+ };
+ };
+ };
+
+ dmic@2904200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic3_ep>;
+ };
+ };
+
+ dmic3_port: port@1 {
+ reg = <1>;
+
+ dmic3_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ mvc@290a000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_in_ep>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc1_out_ep>;
+ };
+ };
+ };
+ };
+
+ mvc@290a200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_in_ep>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_mvc2_out_ep>;
+ };
+ };
+ };
+ };
+
+ amixer@290bb00 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ mixer_in1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ mixer_in2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mixer_in3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mixer_in4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mixer_in5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mixer_in6_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mixer_in7_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in7_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mixer_in8_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in8_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mixer_in9_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in9_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mixer_in10_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_in10_ep>;
+ };
+ };
+
+ mixer_out1_port: port@a {
+ reg = <0xa>;
+
+ mixer_out1_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out1_ep>;
+ };
+ };
+
+ mixer_out2_port: port@b {
+ reg = <0xb>;
+
+ mixer_out2_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out2_ep>;
+ };
+ };
+
+ mixer_out3_port: port@c {
+ reg = <0xc>;
+
+ mixer_out3_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out3_ep>;
+ };
+ };
+
+ mixer_out4_port: port@d {
+ reg = <0xd>;
+
+ mixer_out4_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out4_ep>;
+ };
+ };
+
+ mixer_out5_port: port@e {
+ reg = <0xe>;
+
+ mixer_out5_ep: endpoint {
+ remote-endpoint = <&xbar_mixer_out5_ep>;
+ };
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+ };
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a40000 {
+ status = "okay";
+ };
+ };
+ };
+
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "serial0:115200n8";
@@ -21,4 +1749,59 @@
serial {
status = "okay";
};
+
+ sound {
+ status = "okay";
+
+ compatible = "nvidia,tegra186-audio-graph-card";
+
+ dais = /* ADMAIF (FE) Ports */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* XBAR Ports */
+ <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+ <&xbar_i2s6_port>, <&xbar_dmic3_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+ <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+ <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+ <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+ <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
+ <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
+ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
+ <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
+ <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&amx3_out_port>, <&amx4_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&adx3_out1_port>, <&adx3_out2_port>,
+ <&adx3_out3_port>, <&adx3_out4_port>,
+ <&adx4_out1_port>, <&adx4_out2_port>,
+ <&adx4_out3_port>, <&adx4_out4_port>,
+ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>,
+ <&mixer_out4_port>, <&mixer_out5_port>,
+ /* BE I/O Ports */
+ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
+ <&dmic3_port>;
+
+ label = "NVIDIA Jetson AGX Orin APE";
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 42658e6..44869c6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -1107,6 +1107,23 @@
status = "disabled";
};
+ sound {
+ status = "disabled";
+
+ clocks = <&bpmp TEGRA234_CLK_PLLA>,
+ <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ clock-names = "pll_a", "plla_out0";
+ assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
+ <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+ <&bpmp TEGRA234_CLK_AUD_MCLK>;
+ assigned-clock-parents = <0>,
+ <&bpmp TEGRA234_CLK_PLLA>,
+ <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_APER &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_APEW &emc>;
+ interconnect-names = "dma-mem", "write";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--
2.7.4
^ permalink raw reply related
* [PATCH v3 4/5] arm64: tegra: Add audio devices on Tegra234
From: Sameer Pujar @ 2022-01-28 12:37 UTC (permalink / raw)
To: broonie, lgirdwood, tiwai, perex, robh+dt, thierry.reding
Cc: jonathanh, mkumard, devicetree, linux-tegra, linux-kernel,
alsa-devel, Sameer Pujar
In-Reply-To: <1643373476-8538-1-git-send-email-spujar@nvidia.com>
Add following devices which are part of APE subsystem
* ACONNECT, AGIC and ADMA
* AHUB and children (ADMAIF, I2S, DMIC, DSPK, MVC, SFC,
AMX, ADX and Mixer)
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 415 +++++++++++++++++++++++++++++++
1 file changed, 415 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 6b6f1580..42658e6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra234-mc.h>
+#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
/ {
@@ -19,6 +20,420 @@
ranges = <0x0 0x0 0x0 0x40000000>;
+ aconnect@2900000 {
+ compatible = "nvidia,tegra234-aconnect",
+ "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA234_CLK_APE>,
+ <&bpmp TEGRA234_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900000 0x02900000 0x200000>;
+ status = "disabled";
+
+ tegra_ahub: ahub@2900800 {
+ compatible = "nvidia,tegra234-ahub";
+ reg = <0x02900800 0x800>;
+ clocks = <&bpmp TEGRA234_CLK_AHUB>;
+ clock-names = "ahub";
+ assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900800 0x02900800 0x11800>;
+ status = "disabled";
+
+ tegra_i2s1: i2s@2901000 {
+ compatible = "nvidia,tegra234-i2s",
+ "nvidia,tegra210-i2s";
+ reg = <0x2901000 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_I2S1>,
+ <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S1";
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@2901100 {
+ compatible = "nvidia,tegra234-i2s",
+ "nvidia,tegra210-i2s";
+ reg = <0x2901100 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_I2S2>,
+ <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S2";
+ status = "disabled";
+ };
+
+ tegra_i2s3: i2s@2901200 {
+ compatible = "nvidia,tegra234-i2s",
+ "nvidia,tegra210-i2s";
+ reg = <0x2901200 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_I2S3>,
+ <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S3";
+ status = "disabled";
+ };
+
+ tegra_i2s4: i2s@2901300 {
+ compatible = "nvidia,tegra234-i2s",
+ "nvidia,tegra210-i2s";
+ reg = <0x2901300 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_I2S4>,
+ <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S4";
+ status = "disabled";
+ };
+
+ tegra_i2s5: i2s@2901400 {
+ compatible = "nvidia,tegra234-i2s",
+ "nvidia,tegra210-i2s";
+ reg = <0x2901400 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_I2S5>,
+ <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S5";
+ status = "disabled";
+ };
+
+ tegra_i2s6: i2s@2901500 {
+ compatible = "nvidia,tegra234-i2s",
+ "nvidia,tegra210-i2s";
+ reg = <0x2901500 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_I2S6>,
+ <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S6";
+ status = "disabled";
+ };
+
+ tegra_sfc1: sfc@2902000 {
+ compatible = "nvidia,tegra234-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902000 0x200>;
+ sound-name-prefix = "SFC1";
+ status = "disabled";
+ };
+
+ tegra_sfc2: sfc@2902200 {
+ compatible = "nvidia,tegra234-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902200 0x200>;
+ sound-name-prefix = "SFC2";
+ status = "disabled";
+ };
+
+ tegra_sfc3: sfc@2902400 {
+ compatible = "nvidia,tegra234-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902400 0x200>;
+ sound-name-prefix = "SFC3";
+ status = "disabled";
+ };
+
+ tegra_sfc4: sfc@2902600 {
+ compatible = "nvidia,tegra234-sfc",
+ "nvidia,tegra210-sfc";
+ reg = <0x2902600 0x200>;
+ sound-name-prefix = "SFC4";
+ status = "disabled";
+ };
+
+ tegra_amx1: amx@2903000 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x2903000 0x100>;
+ sound-name-prefix = "AMX1";
+ status = "disabled";
+ };
+
+ tegra_amx2: amx@2903100 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x2903100 0x100>;
+ sound-name-prefix = "AMX2";
+ status = "disabled";
+ };
+
+ tegra_amx3: amx@2903200 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x2903200 0x100>;
+ sound-name-prefix = "AMX3";
+ status = "disabled";
+ };
+
+ tegra_amx4: amx@2903300 {
+ compatible = "nvidia,tegra234-amx",
+ "nvidia,tegra194-amx";
+ reg = <0x2903300 0x100>;
+ sound-name-prefix = "AMX4";
+ status = "disabled";
+ };
+
+ tegra_adx1: adx@2903800 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903800 0x100>;
+ sound-name-prefix = "ADX1";
+ status = "disabled";
+ };
+
+ tegra_adx2: adx@2903900 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903900 0x100>;
+ sound-name-prefix = "ADX2";
+ status = "disabled";
+ };
+
+ tegra_adx3: adx@2903a00 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903a00 0x100>;
+ sound-name-prefix = "ADX3";
+ status = "disabled";
+ };
+
+ tegra_adx4: adx@2903b00 {
+ compatible = "nvidia,tegra234-adx",
+ "nvidia,tegra210-adx";
+ reg = <0x2903b00 0x100>;
+ sound-name-prefix = "ADX4";
+ status = "disabled";
+ };
+
+
+ tegra_dmic1: dmic@2904000 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x2904000 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC1>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC1";
+ status = "disabled";
+ };
+
+ tegra_dmic2: dmic@2904100 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x2904100 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC2>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC2";
+ status = "disabled";
+ };
+
+ tegra_dmic3: dmic@2904200 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x2904200 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC3>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC3";
+ status = "disabled";
+ };
+
+ tegra_dmic4: dmic@2904300 {
+ compatible = "nvidia,tegra234-dmic",
+ "nvidia,tegra210-dmic";
+ reg = <0x2904300 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DMIC4>;
+ clock-names = "dmic";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC4";
+ status = "disabled";
+ };
+
+ tegra_dspk1: dspk@2905000 {
+ compatible = "nvidia,tegra234-dspk",
+ "nvidia,tegra186-dspk";
+ reg = <0x2905000 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DSPK1>;
+ clock-names = "dspk";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <12288000>;
+ sound-name-prefix = "DSPK1";
+ status = "disabled";
+ };
+
+ tegra_dspk2: dspk@2905100 {
+ compatible = "nvidia,tegra234-dspk",
+ "nvidia,tegra186-dspk";
+ reg = <0x2905100 0x100>;
+ clocks = <&bpmp TEGRA234_CLK_DSPK2>;
+ clock-names = "dspk";
+ assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+ assigned-clock-rates = <12288000>;
+ sound-name-prefix = "DSPK2";
+ status = "disabled";
+ };
+
+ tegra_mvc1: mvc@290a000 {
+ compatible = "nvidia,tegra234-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x290a000 0x200>;
+ sound-name-prefix = "MVC1";
+ status = "disabled";
+ };
+
+ tegra_mvc2: mvc@290a200 {
+ compatible = "nvidia,tegra234-mvc",
+ "nvidia,tegra210-mvc";
+ reg = <0x290a200 0x200>;
+ sound-name-prefix = "MVC2";
+ status = "disabled";
+ };
+
+ tegra_amixer: amixer@290bb00 {
+ compatible = "nvidia,tegra234-amixer",
+ "nvidia,tegra210-amixer";
+ reg = <0x290bb00 0x800>;
+ sound-name-prefix = "MIXER1";
+ status = "disabled";
+ };
+
+ tegra_admaif: admaif@290f000 {
+ compatible = "nvidia,tegra234-admaif",
+ "nvidia,tegra186-admaif";
+ reg = <0x0290f000 0x1000>;
+ dmas = <&adma 1>, <&adma 1>,
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
+ <&adma 4>, <&adma 4>,
+ <&adma 5>, <&adma 5>,
+ <&adma 6>, <&adma 6>,
+ <&adma 7>, <&adma 7>,
+ <&adma 8>, <&adma 8>,
+ <&adma 9>, <&adma 9>,
+ <&adma 10>, <&adma 10>,
+ <&adma 11>, <&adma 11>,
+ <&adma 12>, <&adma 12>,
+ <&adma 13>, <&adma 13>,
+ <&adma 14>, <&adma 14>,
+ <&adma 15>, <&adma 15>,
+ <&adma 16>, <&adma 16>,
+ <&adma 17>, <&adma 17>,
+ <&adma 18>, <&adma 18>,
+ <&adma 19>, <&adma 19>,
+ <&adma 20>, <&adma 20>;
+ dma-names = "rx1", "tx1",
+ "rx2", "tx2",
+ "rx3", "tx3",
+ "rx4", "tx4",
+ "rx5", "tx5",
+ "rx6", "tx6",
+ "rx7", "tx7",
+ "rx8", "tx8",
+ "rx9", "tx9",
+ "rx10", "tx10",
+ "rx11", "tx11",
+ "rx12", "tx12",
+ "rx13", "tx13",
+ "rx14", "tx14",
+ "rx15", "tx15",
+ "rx16", "tx16",
+ "rx17", "tx17",
+ "rx18", "tx18",
+ "rx19", "tx19",
+ "rx20", "tx20";
+ status = "disabled";
+ };
+ };
+
+ adma: dma-controller@2930000 {
+ compatible = "nvidia,tegra234-adma",
+ "nvidia,tegra186-adma";
+ reg = <0x02930000 0x20000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA234_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: interrupt-controller@2a40000 {
+ compatible = "nvidia,tegra234-agic",
+ "nvidia,tegra210-agic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x02a41000 0x1000>,
+ <0x02a42000 0x2000>;
+ interrupts = <GIC_SPI 145
+ (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA234_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
+
misc@100000 {
compatible = "nvidia,tegra234-misc";
reg = <0x00100000 0xf000>,
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/5] dt-bindings: Document Tegra234 APE support
From: Sameer Pujar @ 2022-01-28 12:37 UTC (permalink / raw)
To: broonie, lgirdwood, tiwai, perex, robh+dt, thierry.reding
Cc: jonathanh, mkumard, devicetree, linux-tegra, linux-kernel,
alsa-devel, Sameer Pujar
In-Reply-To: <1643373476-8538-1-git-send-email-spujar@nvidia.com>
Update binding docs for devices which are part of APE subsystem
on Tegra234 chip.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml | 1 +
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 4 +++-
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml | 4 +++-
Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml | 4 +++-
Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml | 3 +++
Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml | 1 +
Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml | 1 +
13 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml
index 7b1a08c..d3ed048 100644
--- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml
@@ -21,6 +21,7 @@ properties:
- const: nvidia,tegra210-aconnect
- items:
- enum:
+ - nvidia,tegra234-aconnect
- nvidia,tegra186-aconnect
- nvidia,tegra194-aconnect
- const: nvidia,tegra210-aconnect
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
index 5c2e2f1..fef8045 100644
--- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
@@ -23,7 +23,9 @@ properties:
- nvidia,tegra210-adma
- nvidia,tegra186-adma
- items:
- - const: nvidia,tegra194-adma
+ - enum:
+ - nvidia,tegra234-adma
+ - nvidia,tegra194-adma
- const: nvidia,tegra186-adma
reg:
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
index ba282f4..62219a5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
@@ -58,6 +58,7 @@ properties:
- enum:
- nvidia,tegra186-agic
- nvidia,tegra194-agic
+ - nvidia,tegra234-agic
- const: nvidia,tegra210-agic
interrupt-controller: true
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml
index 0912d3e..73b98b2 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml
@@ -28,7 +28,9 @@ properties:
oneOf:
- const: nvidia,tegra186-dspk
- items:
- - const: nvidia,tegra194-dspk
+ - enum:
+ - nvidia,tegra234-dspk
+ - nvidia,tegra194-dspk
- const: nvidia,tegra186-dspk
reg:
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
index 19eaacc..372043e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml
@@ -27,7 +27,9 @@ properties:
- nvidia,tegra210-admaif
- nvidia,tegra186-admaif
- items:
- - const: nvidia,tegra194-admaif
+ - enum:
+ - nvidia,tegra234-admaif
+ - nvidia,tegra194-admaif
- const: nvidia,tegra186-admaif
reg:
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml
index c4ba12e..8d8dc7f 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-adx.yaml
@@ -30,6 +30,7 @@ properties:
- const: nvidia,tegra210-adx
- items:
- enum:
+ - nvidia,tegra234-adx
- nvidia,tegra194-adx
- nvidia,tegra186-adx
- const: nvidia,tegra210-adx
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
index df81d20..4727f1e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml
@@ -26,6 +26,7 @@ properties:
- enum:
- nvidia,tegra210-ahub
- nvidia,tegra186-ahub
+ - nvidia,tegra234-ahub
- items:
- const: nvidia,tegra194-ahub
- const: nvidia,tegra186-ahub
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml
index bb2111a..f9e4fc6 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-amx.yaml
@@ -31,6 +31,9 @@ properties:
- const: nvidia,tegra186-amx
- const: nvidia,tegra210-amx
- const: nvidia,tegra194-amx
+ - items:
+ - const: nvidia,tegra234-amx
+ - const: nvidia,tegra194-amx
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml
index 62db982..bcb496d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml
@@ -28,6 +28,7 @@ properties:
- const: nvidia,tegra210-dmic
- items:
- enum:
+ - nvidia,tegra234-dmic
- nvidia,tegra194-dmic
- nvidia,tegra186-dmic
- const: nvidia,tegra210-dmic
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml
index f954be6..6188f56 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml
@@ -28,6 +28,7 @@ properties:
- const: nvidia,tegra210-i2s
- items:
- enum:
+ - nvidia,tegra234-i2s
- nvidia,tegra194-i2s
- nvidia,tegra186-i2s
- const: nvidia,tegra210-i2s
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml
index 428f3c8..ee1e1d2 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mixer.yaml
@@ -28,6 +28,7 @@ properties:
- const: nvidia,tegra210-amixer
- items:
- enum:
+ - nvidia,tegra234-amixer
- nvidia,tegra194-amixer
- nvidia,tegra186-amixer
- const: nvidia,tegra210-amixer
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml
index e2f5a85..c9888c5 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-mvc.yaml
@@ -31,6 +31,7 @@ properties:
- const: nvidia,tegra210-mvc
- items:
- enum:
+ - nvidia,tegra234-mvc
- nvidia,tegra194-mvc
- nvidia,tegra186-mvc
- const: nvidia,tegra210-mvc
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml
index 41ad6517..8579306 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-sfc.yaml
@@ -28,6 +28,7 @@ properties:
- const: nvidia,tegra210-sfc
- items:
- enum:
+ - nvidia,tegra234-sfc
- nvidia,tegra194-sfc
- nvidia,tegra186-sfc
- const: nvidia,tegra210-sfc
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/5] dt-bindings: Add Tegra234 APE support
From: Sameer Pujar @ 2022-01-28 12:37 UTC (permalink / raw)
To: broonie, lgirdwood, tiwai, perex, robh+dt, thierry.reding
Cc: jonathanh, mkumard, devicetree, linux-tegra, linux-kernel,
alsa-devel, Sameer Pujar
In-Reply-To: <1643373476-8538-1-git-send-email-spujar@nvidia.com>
Add clocks, power-domain and memory bindings to support APE subsystem
on Tegra234.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 74 +++++++++++++++++++++++++-
include/dt-bindings/memory/tegra234-mc.h | 7 +++
include/dt-bindings/power/tegra234-powergate.h | 9 ++++
3 files changed, 89 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/power/tegra234-powergate.h
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 8d7e66e..635b5fb 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
@@ -9,6 +9,26 @@
* @defgroup bpmp_clock_ids Clock ID's
* @{
*/
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
+#define TEGRA234_CLK_AHUB 4U
+/** @brief output of gate CLK_ENB_APB2APE */
+#define TEGRA234_CLK_APB2APE 5U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
+#define TEGRA234_CLK_APE 6U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
+#define TEGRA234_CLK_AUD_MCLK 7U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
+#define TEGRA234_CLK_DMIC1 15U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
+#define TEGRA234_CLK_DMIC2 16U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
+#define TEGRA234_CLK_DMIC3 17U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
+#define TEGRA234_CLK_DMIC4 18U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
+#define TEGRA234_CLK_DSPK1 29U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
+#define TEGRA234_CLK_DSPK2 30U
/**
* @brief controls the EMC clock frequency.
* @details Doing a clk_set_rate on this clock will select the
@@ -20,8 +40,60 @@
#define TEGRA234_CLK_EMC 31U
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA234_CLK_FUSE 40U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
+#define TEGRA234_CLK_I2S1 56U
+/** @brief clock recovered from I2S1 input */
+#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
+#define TEGRA234_CLK_I2S2 58U
+/** @brief clock recovered from I2S2 input */
+#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
+#define TEGRA234_CLK_I2S3 60U
+/** @brief clock recovered from I2S3 input */
+#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
+#define TEGRA234_CLK_I2S4 62U
+/** @brief clock recovered from I2S4 input */
+#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
+#define TEGRA234_CLK_I2S5 64U
+/** @brief clock recovered from I2S5 input */
+#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
+#define TEGRA234_CLK_I2S6 66U
+/** @brief clock recovered from I2S6 input */
+#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U
+/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
+#define TEGRA234_CLK_PLLA 93U
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
+#define TEGRA234_CLK_PLLA_OUT0 104U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA234_CLK_SDMMC4 123U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
+#define TEGRA234_CLK_SYNC_DMIC1 139U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
+#define TEGRA234_CLK_SYNC_DMIC2 140U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
+#define TEGRA234_CLK_SYNC_DMIC3 141U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
+#define TEGRA234_CLK_SYNC_DMIC4 142U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
+#define TEGRA234_CLK_SYNC_DSPK1 143U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
+#define TEGRA234_CLK_SYNC_DSPK2 144U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
+#define TEGRA234_CLK_SYNC_I2S1 145U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
+#define TEGRA234_CLK_SYNC_I2S2 146U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
+#define TEGRA234_CLK_SYNC_I2S3 147U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
+#define TEGRA234_CLK_SYNC_I2S4 148U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
+#define TEGRA234_CLK_SYNC_I2S5 149U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
+#define TEGRA234_CLK_SYNC_I2S6 150U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
#define TEGRA234_CLK_UARTA 155U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index 2662f70..444e62d 100644
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -1,4 +1,5 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
@@ -7,6 +8,8 @@
#define TEGRA234_SID_INVALID 0x00
#define TEGRA234_SID_PASSTHROUGH 0x7f
+/* NISO0 stream IDs */
+#define TEGRA234_SID_APE 0x02
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
@@ -20,6 +23,10 @@
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
/* sdmmcd memory write client */
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
+/* Audio Processing (APE) engine read clients */
+#define TEGRA234_MEMORY_CLIENT_APER 0x7a
+/* Audio Processing (APE) engine write clients */
+#define TEGRA234_MEMORY_CLIENT_APEW 0x7b
/* BPMP read client */
#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
/* BPMP write client */
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
new file mode 100644
index 00000000..8e28fcb
--- /dev/null
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
+#define __ABI_MACH_T234_POWERGATE_T234_H_
+
+#define TEGRA234_POWER_DOMAIN_AUD 2U
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/5] ASoC: tegra: Update AHUB driver for Tegra234
From: Sameer Pujar @ 2022-01-28 12:37 UTC (permalink / raw)
To: broonie, lgirdwood, tiwai, perex, robh+dt, thierry.reding
Cc: jonathanh, mkumard, devicetree, linux-tegra, linux-kernel,
alsa-devel, Sameer Pujar
In-Reply-To: <1643373476-8538-1-git-send-email-spujar@nvidia.com>
From: Mohan Kumar <mkumard@nvidia.com>
The register offsets of switches connecting various AHUB internal
modules have changed from previous chip. Address this variation by
making use of Tegra234 based compatible.
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
sound/soc/tegra/tegra210_ahub.c | 146 +++++++++++++++++++++++++++++++++++++++-
sound/soc/tegra/tegra210_ahub.h | 4 +-
2 files changed, 148 insertions(+), 2 deletions(-)
diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahub.c
index 388b815..bccf8b8 100644
--- a/sound/soc/tegra/tegra210_ahub.c
+++ b/sound/soc/tegra/tegra210_ahub.c
@@ -2,7 +2,7 @@
//
// tegra210_ahub.c - Tegra210 AHUB driver
//
-// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
+// Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
#include <linux/clk.h>
#include <linux/device.h>
@@ -624,6 +624,34 @@ MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27);
MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28);
MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29);
+/* Controls for t234 */
+MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44);
+MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45);
+MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48);
+MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49);
+MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a);
+MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b);
+MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c);
+MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d);
+MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e);
+MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f);
+MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50);
+MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51);
+MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52);
+MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53);
+MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58);
+MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59);
+MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a);
+MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b);
+MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c);
+MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d);
+MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e);
+MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f);
+MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60);
+MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61);
+MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62);
+MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63);
+
/*
* The number of entries in, and order of, this array is closely tied to the
* calculation of tegra210_ahub_codec.num_dapm_widgets near the end of
@@ -787,6 +815,102 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
TX_WIDGETS("MIXER1 TX5"),
};
+static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
+ WIDGETS("ADMAIF1", t186_admaif1_tx),
+ WIDGETS("ADMAIF2", t186_admaif2_tx),
+ WIDGETS("ADMAIF3", t186_admaif3_tx),
+ WIDGETS("ADMAIF4", t186_admaif4_tx),
+ WIDGETS("ADMAIF5", t186_admaif5_tx),
+ WIDGETS("ADMAIF6", t186_admaif6_tx),
+ WIDGETS("ADMAIF7", t186_admaif7_tx),
+ WIDGETS("ADMAIF8", t186_admaif8_tx),
+ WIDGETS("ADMAIF9", t186_admaif9_tx),
+ WIDGETS("ADMAIF10", t186_admaif10_tx),
+ WIDGETS("ADMAIF11", t186_admaif11_tx),
+ WIDGETS("ADMAIF12", t186_admaif12_tx),
+ WIDGETS("ADMAIF13", t186_admaif13_tx),
+ WIDGETS("ADMAIF14", t186_admaif14_tx),
+ WIDGETS("ADMAIF15", t186_admaif15_tx),
+ WIDGETS("ADMAIF16", t186_admaif16_tx),
+ WIDGETS("ADMAIF17", t234_admaif17_tx),
+ WIDGETS("ADMAIF18", t234_admaif18_tx),
+ WIDGETS("ADMAIF19", t234_admaif19_tx),
+ WIDGETS("ADMAIF20", t234_admaif20_tx),
+ WIDGETS("I2S1", t186_i2s1_tx),
+ WIDGETS("I2S2", t186_i2s2_tx),
+ WIDGETS("I2S3", t186_i2s3_tx),
+ WIDGETS("I2S4", t186_i2s4_tx),
+ WIDGETS("I2S5", t186_i2s5_tx),
+ WIDGETS("I2S6", t186_i2s6_tx),
+ TX_WIDGETS("DMIC1"),
+ TX_WIDGETS("DMIC2"),
+ TX_WIDGETS("DMIC3"),
+ TX_WIDGETS("DMIC4"),
+ WIDGETS("DSPK1", t186_dspk1_tx),
+ WIDGETS("DSPK2", t186_dspk2_tx),
+ WIDGETS("SFC1", t186_sfc1_tx),
+ WIDGETS("SFC2", t186_sfc2_tx),
+ WIDGETS("SFC3", t186_sfc3_tx),
+ WIDGETS("SFC4", t186_sfc4_tx),
+ WIDGETS("MVC1", t234_mvc1_tx),
+ WIDGETS("MVC2", t234_mvc2_tx),
+ WIDGETS("AMX1 RX1", t234_amx11_tx),
+ WIDGETS("AMX1 RX2", t234_amx12_tx),
+ WIDGETS("AMX1 RX3", t234_amx13_tx),
+ WIDGETS("AMX1 RX4", t234_amx14_tx),
+ WIDGETS("AMX2 RX1", t234_amx21_tx),
+ WIDGETS("AMX2 RX2", t234_amx22_tx),
+ WIDGETS("AMX2 RX3", t234_amx23_tx),
+ WIDGETS("AMX2 RX4", t234_amx24_tx),
+ WIDGETS("AMX3 RX1", t234_amx31_tx),
+ WIDGETS("AMX3 RX2", t234_amx32_tx),
+ WIDGETS("AMX3 RX3", t234_amx33_tx),
+ WIDGETS("AMX3 RX4", t234_amx34_tx),
+ WIDGETS("AMX4 RX1", t234_amx41_tx),
+ WIDGETS("AMX4 RX2", t234_amx42_tx),
+ WIDGETS("AMX4 RX3", t234_amx43_tx),
+ WIDGETS("AMX4 RX4", t234_amx44_tx),
+ TX_WIDGETS("AMX1"),
+ TX_WIDGETS("AMX2"),
+ TX_WIDGETS("AMX3"),
+ TX_WIDGETS("AMX4"),
+ WIDGETS("ADX1", t234_adx1_tx),
+ WIDGETS("ADX2", t234_adx2_tx),
+ WIDGETS("ADX3", t234_adx3_tx),
+ WIDGETS("ADX4", t234_adx4_tx),
+ TX_WIDGETS("ADX1 TX1"),
+ TX_WIDGETS("ADX1 TX2"),
+ TX_WIDGETS("ADX1 TX3"),
+ TX_WIDGETS("ADX1 TX4"),
+ TX_WIDGETS("ADX2 TX1"),
+ TX_WIDGETS("ADX2 TX2"),
+ TX_WIDGETS("ADX2 TX3"),
+ TX_WIDGETS("ADX2 TX4"),
+ TX_WIDGETS("ADX3 TX1"),
+ TX_WIDGETS("ADX3 TX2"),
+ TX_WIDGETS("ADX3 TX3"),
+ TX_WIDGETS("ADX3 TX4"),
+ TX_WIDGETS("ADX4 TX1"),
+ TX_WIDGETS("ADX4 TX2"),
+ TX_WIDGETS("ADX4 TX3"),
+ TX_WIDGETS("ADX4 TX4"),
+ WIDGETS("MIXER1 RX1", t186_mixer11_tx),
+ WIDGETS("MIXER1 RX2", t186_mixer12_tx),
+ WIDGETS("MIXER1 RX3", t186_mixer13_tx),
+ WIDGETS("MIXER1 RX4", t186_mixer14_tx),
+ WIDGETS("MIXER1 RX5", t186_mixer15_tx),
+ WIDGETS("MIXER1 RX6", t186_mixer16_tx),
+ WIDGETS("MIXER1 RX7", t186_mixer17_tx),
+ WIDGETS("MIXER1 RX8", t186_mixer18_tx),
+ WIDGETS("MIXER1 RX9", t186_mixer19_tx),
+ WIDGETS("MIXER1 RX10", t186_mixer110_tx),
+ TX_WIDGETS("MIXER1 TX1"),
+ TX_WIDGETS("MIXER1 TX2"),
+ TX_WIDGETS("MIXER1 TX3"),
+ TX_WIDGETS("MIXER1 TX4"),
+ TX_WIDGETS("MIXER1 TX5"),
+};
+
#define TEGRA_COMMON_MUX_ROUTES(name) \
{ name " XBAR-TX", NULL, name " Mux" }, \
{ name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \
@@ -1027,6 +1151,13 @@ static const struct snd_soc_component_driver tegra186_ahub_component = {
.num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
};
+static const struct snd_soc_component_driver tegra234_ahub_component = {
+ .dapm_widgets = tegra234_ahub_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets),
+ .dapm_routes = tegra186_ahub_routes,
+ .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
+};
+
static const struct regmap_config tegra210_ahub_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -1067,9 +1198,22 @@ static const struct tegra_ahub_soc_data soc_data_tegra186 = {
.reg_count = TEGRA186_XBAR_UPDATE_MAX_REG,
};
+static const struct tegra_ahub_soc_data soc_data_tegra234 = {
+ .cmpnt_drv = &tegra234_ahub_component,
+ .dai_drv = tegra186_ahub_dais,
+ .num_dais = ARRAY_SIZE(tegra186_ahub_dais),
+ .regmap_config = &tegra186_ahub_regmap_config,
+ .mask[0] = TEGRA186_XBAR_REG_MASK_0,
+ .mask[1] = TEGRA186_XBAR_REG_MASK_1,
+ .mask[2] = TEGRA186_XBAR_REG_MASK_2,
+ .mask[3] = TEGRA186_XBAR_REG_MASK_3,
+ .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG,
+};
+
static const struct of_device_id tegra_ahub_of_match[] = {
{ .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
{ .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
+ { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 },
{},
};
MODULE_DEVICE_TABLE(of, tegra_ahub_of_match);
diff --git a/sound/soc/tegra/tegra210_ahub.h b/sound/soc/tegra/tegra210_ahub.h
index 47802bbe..2728db4 100644
--- a/sound/soc/tegra/tegra210_ahub.h
+++ b/sound/soc/tegra/tegra210_ahub.h
@@ -2,7 +2,7 @@
/*
* tegra210_ahub.h - TEGRA210 AHUB
*
- * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
*/
@@ -74,6 +74,8 @@
tegra_ahub_get_value_enum, \
tegra_ahub_put_value_enum)
+#define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id)
+
#define WIDGETS(sname, ename) \
SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/5] Tegra234 APE support
From: Sameer Pujar @ 2022-01-28 12:37 UTC (permalink / raw)
To: broonie, lgirdwood, tiwai, perex, robh+dt, thierry.reding
Cc: jonathanh, mkumard, devicetree, linux-tegra, linux-kernel,
alsa-devel, Sameer Pujar
This adds APE support on Tegra234 and enables sound card on
Jetson AGX Orin platform.
Changelog
=========
v2->v3
------
* Fixed DT build error related to power-domain and
iommu reference.
Reported-by: kernel test robot <lkp@intel.com>
v1->v2
------
* Rebased patches on latest linux-next
Mohan Kumar (1):
ASoC: tegra: Update AHUB driver for Tegra234
Sameer Pujar (4):
dt-bindings: Add Tegra234 APE support
dt-bindings: Document Tegra234 APE support
arm64: tegra: Add audio devices on Tegra234
arm64: tegra: APE sound card for Jetson AGX Orin
.../bindings/bus/nvidia,tegra210-aconnect.yaml | 1 +
.../bindings/dma/nvidia,tegra210-adma.yaml | 4 +-
.../bindings/interrupt-controller/arm,gic.yaml | 1 +
.../bindings/sound/nvidia,tegra186-dspk.yaml | 4 +-
.../bindings/sound/nvidia,tegra210-admaif.yaml | 4 +-
.../bindings/sound/nvidia,tegra210-adx.yaml | 1 +
.../bindings/sound/nvidia,tegra210-ahub.yaml | 1 +
.../bindings/sound/nvidia,tegra210-amx.yaml | 3 +
.../bindings/sound/nvidia,tegra210-dmic.yaml | 1 +
.../bindings/sound/nvidia,tegra210-i2s.yaml | 1 +
.../bindings/sound/nvidia,tegra210-mixer.yaml | 1 +
.../bindings/sound/nvidia,tegra210-mvc.yaml | 1 +
.../bindings/sound/nvidia,tegra210-sfc.yaml | 1 +
.../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 1783 ++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 432 +++++
include/dt-bindings/clock/tegra234-clock.h | 74 +-
include/dt-bindings/memory/tegra234-mc.h | 7 +
include/dt-bindings/power/tegra234-powergate.h | 9 +
sound/soc/tegra/tegra210_ahub.c | 146 +-
sound/soc/tegra/tegra210_ahub.h | 4 +-
20 files changed, 2473 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/power/tegra234-powergate.h
--
2.7.4
^ permalink raw reply
* Re: [PATCH v2 1/2] mtd: rawnand: meson: discard the common MMC sub clock framework
From: Liang Yang @ 2022-01-28 12:16 UTC (permalink / raw)
To: Miquel Raynal
Cc: linux-mtd, Rob Herring, Richard Weinberger, Vignesh Raghavendra,
Jerome Brunet, Neil Armstrong, Martin Blumenstingl, Kevin Hilman,
Jianxin Pan, Victor Wan, XianWei Zhao, Kelvin Zhang, BiChao Zheng,
YongHui Yu, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree
In-Reply-To: <20220128124036.25fe0539@xps13>
Hi Miquel,
Thanks for the review and quick response.
On 2022/1/28 19:40, Miquel Raynal wrote:
> [ EXTERNAL EMAIL ]
>
> Hi Liang,
>
> liang.yang@amlogic.com wrote on Fri, 28 Jan 2022 19:32:36 +0800:
>
>> EMMC and NAND has the same clock control register named 'SD_EMMC_CLOCK' which is
>
> have
ok
>
>> defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and
>> bit6~7 is the mux for fix pll and xtal.
>
>> Previously a common MMC sub clock framework is implemented and shared by EMMC and
>
> I believe you meant that this hasa already been contributed? I would
> then rephrase with:
>
> A common MMC and NAND sub-clock has been implemented and can be used by
> the eMMC and NAND controller (which are mutually exclusive anyway).
>
> Let's use this new clock.
ok. thanks
>
>> NAND, but that is coupling the EMMC and NAND, although EMMC and NAND is mutually
>> exclusive.
>>
>> Change-Id: Ibeb4c7ff886f5886aac4d6c664d7bbd1b1bcb997
>
> No change Ids.
ok. i will delete next version.
>
>> Signed-off-by: Liang Yang <liang.yang@amlogic.com>
>> ---
>> drivers/mtd/nand/raw/meson_nand.c | 161 +++++++++++++++++-------------
>> 1 file changed, 89 insertions(+), 72 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
>> index ac3be92872d0..f6a3d5c2ea1c 100644
>> --- a/drivers/mtd/nand/raw/meson_nand.c
>> +++ b/drivers/mtd/nand/raw/meson_nand.c
>> @@ -2,7 +2,7 @@
>> /*
>> * Amlogic Meson Nand Flash Controller Driver
>> *
>> - * Copyright (c) 2018 Amlogic, inc.
>> + * Copyright (c) 2018-2021 Amlogic, inc.
>
> Please don't.
>
>> * Author: Liang Yang <liang.yang@amlogic.com>
>> */
>>
>> @@ -10,6 +10,7 @@
>> #include <linux/dma-mapping.h>
>> #include <linux/interrupt.h>
>> #include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> #include <linux/mtd/rawnand.h>
>> #include <linux/mtd/mtd.h>
>> #include <linux/mfd/syscon.h>
>> @@ -19,6 +20,7 @@
>> #include <linux/iopoll.h>
>> #include <linux/of.h>
>> #include <linux/of_device.h>
>> +#include <linux/of_address.h>
>> #include <linux/sched/task_stack.h>
>>
>> #define NFC_REG_CMD 0x00
>> @@ -104,6 +106,9 @@
>>
>> #define PER_INFO_BYTE 8
>>
>> +#define CLK_DIV_SHIFT 0
>> +#define CLK_DIV_WIDTH 6
>> +
>> struct meson_nfc_nand_chip {
>> struct list_head node;
>> struct nand_chip nand;
>> @@ -151,15 +156,17 @@ struct meson_nfc {
>> struct nand_controller controller;
>> struct clk *core_clk;
>> struct clk *device_clk;
>> - struct clk *phase_tx;
>> - struct clk *phase_rx;
>> + struct clk *nand_clk;
>> + struct clk_divider nand_divider;
>>
>> unsigned long clk_rate;
>> u32 bus_timing;
>>
>> struct device *dev;
>> - void __iomem *reg_base;
>> - struct regmap *reg_clk;
>> + struct {
>> + void __iomem *reg_base;
>> + void __iomem *sd_emmc_clock;
>> + } res;
>
> Please split your commit: first the mechanical changes, then the use of
> the new area or something like that.
>
> Otherwise there are too many lines changed, I can't spot where it is
> interesting.
ok. i will split it next version. thanks.
>
> Thanks,
> Miquèl
>
> .
^ permalink raw reply
* Re: [PATCH v2 02/19] ath11k: Refactor PCI code to support hybrid bus devices
From: Kalle Valo @ 2022-01-28 12:13 UTC (permalink / raw)
To: Manikanta Pubbisetty; +Cc: ath11k, linux-wireless, devicetree, robh
In-Reply-To: <1642337235-8618-3-git-send-email-quic_mpubbise@quicinc.com>
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> writes:
> Unlike other ATH11K PCIe devices which are enumerated by APSS
> processor (Application Processor SubSystem), WCN6750 gets
> enumerated by the WPSS Q6 processor (Wireless Processor SubSystem);
> In simple terms, though WCN6750 is PCIe device, it is not attached
> to the APSS processor, APSS will not know of such a device being
> present in the system and therefore WCN6750 will be registered as
> a platform device to the kernel core like other supported AHB
> devices.
>
> WCN6750 uses both AHB and PCI APIs for it's operation, it uses
> AHB APIs for device probe/boot and PCI APIs for device setup
> and register accesses; Because of this nature, it is referred
> as a hybrid bus device.
>
> Refactor PCI code to support hybrid bus devices like WCN6750.
>
> Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00573-QCAMSLSWPLZ-1
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1
> Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
[...]
> --- /dev/null
> +++ b/drivers/net/wireless/ath/ath11k/pci_cmn.c
[...]
> +static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
> +{
> + struct ath11k_base *ab = ab_pci->ab;
> +
> + u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
> +
> + lockdep_assert_held(&ab_pci->window_lock);
> +
> + if (window != ab_pci->register_window) {
> + iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
> + ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
> + ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
> + ab_pci->register_window = window;
> + }
> +}
So the style used in ath11k is ath11k_<filename>_foo, so that a function
ath11k_pci_foo() should be in pci.c. This patch is now breaking that
style. Maybe pci_cmn.c should renamed to cpci.c, pcic.c or something
like that? Then the function prefix could be ath11k_cpci_, ath11k_pcic_
or similar.
--
https://patchwork.kernel.org/project/linux-wireless/list/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* [PATCH v1, 3/4] drm/mediatek: split postmask component
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-1-yongqiang.niu@mediatek.com>
add postmask private data for differnt soc support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 155 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 170 insertions(+), 27 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..f26fe646ee2a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
+ mtk_disp_postmask.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp_comp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..f4c21195c3ea 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -81,6 +81,14 @@ void mtk_ovl_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_ovl_disable_vblank(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev);
+void mtk_postmask_clk_disable(struct device *dev);
+void mtk_postmask_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_postmask_start(struct device *dev);
+void mtk_postmask_stop(struct device *dev);
+
void mtk_rdma_bypass_shadow(struct device *dev);
int mtk_rdma_clk_enable(struct device *dev);
void mtk_rdma_clk_disable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
new file mode 100644
index 000000000000..fc04b445c2ed
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_POSTMASK_EN 0x0000
+#define POSTMASK_EN BIT(0)
+#define DISP_POSTMASK_CFG 0x0020
+#define POSTMASK_RELAY_MODE BIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
+struct mtk_disp_postmask_data {
+ u32 reserved;
+};
+
+/*
+ * struct mtk_disp_postmask - DISP_POSTMASK driver structure
+ */
+struct mtk_disp_postmask {
+ struct clk *clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+ const struct mtk_disp_postmask_data *data;
+};
+
+int mtk_postmask_clk_enable(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(postmask->clk);
+}
+
+void mtk_postmask_clk_disable(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(postmask->clk);
+}
+
+void mtk_postmask_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,
+ DISP_POSTMASK_SIZE);
+ mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,
+ postmask->regs, DISP_POSTMASK_CFG);
+}
+
+void mtk_postmask_start(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
+}
+
+void mtk_postmask_stop(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
+}
+
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_postmask_component_ops = {
+ .bind = mtk_disp_postmask_bind,
+ .unbind = mtk_disp_postmask_unbind,
+};
+
+static int mtk_disp_postmask_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_postmask *priv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get postmask clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap postmask\n");
+ return PTR_ERR(priv->regs);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->data = of_device_get_match_data(dev);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_postmask_component_ops);
+ if (ret)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_postmask_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8192-disp-postmask"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+
+struct platform_driver mtk_disp_postmask_driver = {
+ .probe = mtk_disp_postmask_probe,
+ .remove = mtk_disp_postmask_remove,
+ .driver = {
+ .name = "mediatek-disp-postmask",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_postmask_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b4b682bc1991..e02fc8dcad91 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -199,31 +199,6 @@ static void mtk_od_start(struct device *dev)
writel(1, priv->regs + DISP_REG_OD_EN);
}
-static void mtk_postmask_config(struct device *dev, unsigned int w,
- unsigned int h, unsigned int vrefresh,
- unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
- DISP_REG_POSTMASK_SIZE);
- mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
- priv->regs, DISP_REG_POSTMASK_CFG);
-}
-
-static void mtk_postmask_start(struct device *dev)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
-}
-
-static void mtk_postmask_stop(struct device *dev)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
-}
static void mtk_ufoe_start(struct device *dev)
{
@@ -308,8 +283,8 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
};
static const struct mtk_ddp_comp_funcs ddp_postmask = {
- .clk_enable = mtk_ddp_clk_enable,
- .clk_disable = mtk_ddp_clk_disable,
+ .clk_enable = mtk_postmask_clk_enable,
+ .clk_disable = mtk_postmask_clk_disable,
.config = mtk_postmask_config,
.start = mtk_postmask_start,
.stop = mtk_postmask_stop,
@@ -510,6 +485,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_GAMMA ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_POSTMASK ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 56ff8c57ef8f..6efb423ccc92 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -609,6 +609,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_POSTMASK ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -709,6 +710,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_ovl_driver,
+ &mtk_disp_postmask_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..c1e676aebe57 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_disp_postmask_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
--
2.25.1
^ permalink raw reply related
* [PATCH v1, 4/4] drm/mediatek: add mt8186 display support
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-1-yongqiang.niu@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 ++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6efb423ccc92..754b1be25d0d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -158,6 +158,24 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI0,
+};
+
static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
@@ -221,6 +239,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
+ .main_path = mt8186_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
+ .ext_path = mt8186_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -463,6 +488,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8186-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
@@ -475,14 +502,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8186-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8192-disp-ovl",
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8186-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt8192-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt8192-disp-postmask",
.data = (void *)MTK_DISP_POSTMASK },
+ { .compatible = "mediatek,mt8186-disp-postmask",
+ .data = (void *)MTK_DISP_POSTMASK},
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8167-disp-pwm",
@@ -511,12 +544,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8183-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8186-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8183-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8186-dsi",
+ .data = (void *)MTK_DSI },
{ }
};
@@ -533,6 +570,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8186-mmsys",
+ .data = &mt8186_mmsys_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
{ }
--
2.25.1
^ permalink raw reply related
* [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-1-yongqiang.niu@mediatek.com>
Add mtk mutex support for MT8186 SoC.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 45 ++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2ca55bb5a8be..ebd95fd0f36e 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -26,6 +26,23 @@
#define INT_MUTEX BIT(1)
+#define MT8186_MUTEX_MOD_DISP_OVL0 0
+#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
+#define MT8186_MUTEX_MOD_DISP_RDMA0 2
+#define MT8186_MUTEX_MOD_DISP_COLOR0 4
+#define MT8186_MUTEX_MOD_DISP_CCORR0 5
+#define MT8186_MUTEX_MOD_DISP_AAL0 7
+#define MT8186_MUTEX_MOD_DISP_GAMMA0 8
+#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
+#define MT8186_MUTEX_MOD_DISP_DITHER0 10
+#define MT8186_MUTEX_MOD_DISP_RDMA1 17
+
+#define MT8186_MUTEX_SOF_SINGLE_MODE 0
+#define MT8186_MUTEX_SOF_DSI0 1
+#define MT8186_MUTEX_SOF_DPI0 2
+#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
+#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
+
#define MT8167_MUTEX_MOD_DISP_PWM 1
#define MT8167_MUTEX_MOD_DISP_OVL0 6
#define MT8167_MUTEX_MOD_DISP_OVL1 7
@@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
+ [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
+};
+
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
@@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
+static const struct mtk_mutex_data mt8186_mutex_driver_data = {
+ .mutex_mod = mt8186_mutex_mod,
+ .mutex_sof = mt8186_mutex_sof,
+ .mutex_mod_reg = MT8183_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_MUTEX0_SOF0,
+};
+
static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_mod = mt8192_mutex_mod,
.mutex_sof = mt8183_mutex_sof,
@@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
+ { .compatible = "mediatek,mt8186-disp-mutex",
+ .data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
{},
--
2.25.1
^ permalink raw reply related
* [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-1-yongqiang.niu@mediatek.com>
mt8186 routing registers is different with other Soc
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 +++
2 files changed, 124 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
new file mode 100644
index 000000000000..7de329f2d729
--- /dev/null
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
+#define __SOC_MEDIATEK_MT8186_MMSYS_H
+
+#define MT8186_MMSYS_OVL_CON 0xF04
+#define MT8186_MMSYS_OVL0_CON_MASK 0x3
+#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
+#define MT8186_OVL0_GO_BLEND BIT(0)
+#define MT8186_OVL0_GO_BG BIT(1)
+#define MT8186_OVL0_2L_GO_BLEND BIT(2)
+#define MT8186_OVL0_2L_GO_BG BIT(3)
+#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
+#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
+#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
+#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
+#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
+#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
+#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
+#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
+#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
+#define MT8186_DISP_OVL0_MOUT_EN 0xF18
+#define MT8186_OVL0_MOUT_EN_MASK 0xF
+#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
+#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
+#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
+#define MT8186_DITHER0_MOUT_EN_MASK 0xF
+#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
+#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
+#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
+#define MT8186_DISP_RDMA0_SEL_IN 0xF28
+#define MT8186_RDMA0_SEL_IN_MASK 0xF
+#define MT8186_RDMA0_FROM_OVL0 0
+#define MT8186_RDMA0_FROM_OVL0_2L 2
+#define MT8186_DISP_DSI0_SEL_IN 0xF30
+#define MT8186_DSI0_SEL_IN_MASK 0xF
+#define MT8186_DSI0_FROM_RDMA0 0
+#define MT8186_DSI0_FROM_DITHER0 1
+#define MT8186_DSI0_FROM_RDMA1 2
+#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
+#define MT8186_RDMA1_MOUT_EN_MASK 0xF
+#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
+#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
+#define MT8186_DISP_RDMA1_SEL_IN 0xF40
+#define MT8186_RDMA1_SEL_IN_MASK 0xF
+#define MT8186_RDMA1_FROM_OVL0 0
+#define MT8186_RDMA1_FROM_OVL0_2L 2
+#define MT8186_RDMA1_FROM_DITHER0 3
+#define MT8186_DISP_DPI0_SEL_IN 0xF44
+#define MT8186_DPI0_SEL_IN_MASK 0xF
+#define MT8186_DPI0_FROM_RDMA1 0
+#define MT8186_DPI0_FROM_DITHER0 1
+#define MT8186_DPI0_FROM_RDMA0 2
+
+static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
+ MT8186_OVL0_MOUT_TO_RDMA0
+ },
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
+ MT8186_RDMA0_FROM_OVL0
+ },
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
+ MT8186_OVL0_GO_BLEND
+ },
+ {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
+ MT8186_RDMA0_SOUT_TO_COLOR0
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
+ MT8186_DITHER0_MOUT_TO_DSI0,
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
+ MT8186_DSI0_FROM_DITHER0
+ },
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
+ MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
+ MT8186_OVL0_2L_MOUT_TO_RDMA1
+ },
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
+ MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
+ MT8186_RDMA1_FROM_OVL0_2L
+ },
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
+ MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
+ MT8186_OVL0_2L_GO_BLEND
+ },
+ {
+ DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
+ MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
+ MT8186_RDMA1_MOUT_TO_DPI0_SEL
+ },
+ {
+ DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
+ MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
+ MT8186_DPI0_FROM_RDMA1
+ },
+};
+
+#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1e448f1ffefb..0da25069ffb3 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -15,6 +15,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
@@ -56,6 +57,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
+ .clk_driver = "clk-mt8186-mm",
+ .routes = mmsys_mt8186_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@@ -242,6 +249,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8186-mmsys",
+ .data = &mt8186_mmsys_driver_data,
+ },
{
.compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data,
--
2.25.1
^ permalink raw reply related
* [PATCH v1, 0/4] add display support for mediatek SOC MT8186
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Yongqiang Niu (4):
soc: mediatek: mmsys: Add mt8186 mmsys routing table
soc: mediatek: add mtk mutex support for MT8186
drm/mediatek: split postmask component
drm/mediatek: add mt8186 display support
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 155 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 41 +++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 ++
drivers/soc/mediatek/mtk-mutex.c | 45 ++++++
9 files changed, 378 insertions(+), 27 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h
--
2.25.1
^ permalink raw reply
* Re: [PATCH v2 1/2] mtd: rawnand: meson: discard the common MMC sub clock framework
From: Miquel Raynal @ 2022-01-28 11:40 UTC (permalink / raw)
To: Liang Yang
Cc: linux-mtd, Rob Herring, Richard Weinberger, Vignesh Raghavendra,
Jerome Brunet, Neil Armstrong, Martin Blumenstingl, Kevin Hilman,
Jianxin Pan, Victor Wan, XianWei Zhao, Kelvin Zhang, BiChao Zheng,
YongHui Yu, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree
In-Reply-To: <20220128113237.39996-2-liang.yang@amlogic.com>
Hi Liang,
liang.yang@amlogic.com wrote on Fri, 28 Jan 2022 19:32:36 +0800:
> EMMC and NAND has the same clock control register named 'SD_EMMC_CLOCK' which is
have
> defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and
> bit6~7 is the mux for fix pll and xtal.
> Previously a common MMC sub clock framework is implemented and shared by EMMC and
I believe you meant that this hasa already been contributed? I would
then rephrase with:
A common MMC and NAND sub-clock has been implemented and can be used by
the eMMC and NAND controller (which are mutually exclusive anyway).
Let's use this new clock.
> NAND, but that is coupling the EMMC and NAND, although EMMC and NAND is mutually
> exclusive.
>
> Change-Id: Ibeb4c7ff886f5886aac4d6c664d7bbd1b1bcb997
No change Ids.
> Signed-off-by: Liang Yang <liang.yang@amlogic.com>
> ---
> drivers/mtd/nand/raw/meson_nand.c | 161 +++++++++++++++++-------------
> 1 file changed, 89 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
> index ac3be92872d0..f6a3d5c2ea1c 100644
> --- a/drivers/mtd/nand/raw/meson_nand.c
> +++ b/drivers/mtd/nand/raw/meson_nand.c
> @@ -2,7 +2,7 @@
> /*
> * Amlogic Meson Nand Flash Controller Driver
> *
> - * Copyright (c) 2018 Amlogic, inc.
> + * Copyright (c) 2018-2021 Amlogic, inc.
Please don't.
> * Author: Liang Yang <liang.yang@amlogic.com>
> */
>
> @@ -10,6 +10,7 @@
> #include <linux/dma-mapping.h>
> #include <linux/interrupt.h>
> #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/mtd/rawnand.h>
> #include <linux/mtd/mtd.h>
> #include <linux/mfd/syscon.h>
> @@ -19,6 +20,7 @@
> #include <linux/iopoll.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/sched/task_stack.h>
>
> #define NFC_REG_CMD 0x00
> @@ -104,6 +106,9 @@
>
> #define PER_INFO_BYTE 8
>
> +#define CLK_DIV_SHIFT 0
> +#define CLK_DIV_WIDTH 6
> +
> struct meson_nfc_nand_chip {
> struct list_head node;
> struct nand_chip nand;
> @@ -151,15 +156,17 @@ struct meson_nfc {
> struct nand_controller controller;
> struct clk *core_clk;
> struct clk *device_clk;
> - struct clk *phase_tx;
> - struct clk *phase_rx;
> + struct clk *nand_clk;
> + struct clk_divider nand_divider;
>
> unsigned long clk_rate;
> u32 bus_timing;
>
> struct device *dev;
> - void __iomem *reg_base;
> - struct regmap *reg_clk;
> + struct {
> + void __iomem *reg_base;
> + void __iomem *sd_emmc_clock;
> + } res;
Please split your commit: first the mechanical changes, then the use of
the new area or something like that.
Otherwise there are too many lines changed, I can't spot where it is
interesting.
Thanks,
Miquèl
^ permalink raw reply
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