* Re: [PATCH v1, 4/4] drm/mediatek: add mt8186 display support
From: Chun-Kuang Hu @ 2022-01-28 16:19 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-5-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 ++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 6efb423ccc92..754b1be25d0d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -158,6 +158,24 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_POSTMASK0,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI0,
> +};
> +
> static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
> DDP_COMPONENT_OVL0,
> DDP_COMPONENT_OVL_2L0,
> @@ -221,6 +239,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> + .main_path = mt8186_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
> + .ext_path = mt8186_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .main_path = mt8192_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
> @@ -463,6 +488,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8186-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-od",
> @@ -475,14 +502,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8183-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8186-disp-ovl",
Add "mediatek,mt8186-disp-ovl" to binding document.
> + .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8192-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8183-disp-ovl-2l",
> .data = (void *)MTK_DISP_OVL_2L },
> + { .compatible = "mediatek,mt8186-disp-ovl-2l",
Ditto.
> + .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt8192-disp-ovl-2l",
> .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt8192-disp-postmask",
> .data = (void *)MTK_DISP_POSTMASK },
> + { .compatible = "mediatek,mt8186-disp-postmask",
Ditto.
> + .data = (void *)MTK_DISP_POSTMASK},
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8167-disp-pwm",
> @@ -511,12 +544,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8183-dpi",
> .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8186-dpi",
Ditto.
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8183-dsi",
> .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8186-dsi",
Ditto.
Regards,
Chun-Kuang.
> + .data = (void *)MTK_DSI },
> { }
> };
>
> @@ -533,6 +570,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
> .data = &mt8173_mmsys_driver_data},
> { .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data},
> + { .compatible = "mediatek,mt8186-mmsys",
> + .data = &mt8186_mmsys_driver_data},
> { .compatible = "mediatek,mt8192-mmsys",
> .data = &mt8192_mmsys_driver_data},
> { }
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186
From: Chun-Kuang Hu @ 2022-01-28 16:17 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-3-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> Add mtk mutex support for MT8186 SoC.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 45 ++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2ca55bb5a8be..ebd95fd0f36e 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -26,6 +26,23 @@
>
> #define INT_MUTEX BIT(1)
>
> +#define MT8186_MUTEX_MOD_DISP_OVL0 0
> +#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
> +#define MT8186_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8186_MUTEX_MOD_DISP_COLOR0 4
> +#define MT8186_MUTEX_MOD_DISP_CCORR0 5
> +#define MT8186_MUTEX_MOD_DISP_AAL0 7
> +#define MT8186_MUTEX_MOD_DISP_GAMMA0 8
> +#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
> +#define MT8186_MUTEX_MOD_DISP_DITHER0 10
> +#define MT8186_MUTEX_MOD_DISP_RDMA1 17
> +
> +#define MT8186_MUTEX_SOF_SINGLE_MODE 0
> +#define MT8186_MUTEX_SOF_DSI0 1
> +#define MT8186_MUTEX_SOF_DPI0 2
> +#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
> +#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
> +
> #define MT8167_MUTEX_MOD_DISP_PWM 1
> #define MT8167_MUTEX_MOD_DISP_OVL0 6
> #define MT8167_MUTEX_MOD_DISP_OVL1 7
> @@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
> + [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
> +};
> +
> static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> @@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8186_mutex_driver_data = {
> + .mutex_mod = mt8186_mutex_mod,
> + .mutex_sof = mt8186_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> +};
> +
> static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_mod = mt8192_mutex_mod,
> .mutex_sof = mt8183_mutex_sof,
> @@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8173_mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = &mt8183_mutex_driver_data},
> + { .compatible = "mediatek,mt8186-disp-mutex",
Add "mediatek,mt8186-disp-mutex" to binding document.
Regards,
Chun-Kuang.
> + .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> {},
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table
From: Chun-Kuang Hu @ 2022-01-28 16:16 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
In-Reply-To: <20220128120718.30545-2-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> mt8186 routing registers is different with other Soc
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 +++
> 2 files changed, 124 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> new file mode 100644
> index 000000000000..7de329f2d729
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -0,0 +1,113 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
> +#define __SOC_MEDIATEK_MT8186_MMSYS_H
> +
> +#define MT8186_MMSYS_OVL_CON 0xF04
> +#define MT8186_MMSYS_OVL0_CON_MASK 0x3
> +#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
> +#define MT8186_OVL0_GO_BLEND BIT(0)
> +#define MT8186_OVL0_GO_BG BIT(1)
> +#define MT8186_OVL0_2L_GO_BLEND BIT(2)
> +#define MT8186_OVL0_2L_GO_BG BIT(3)
> +#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
> +#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
> +#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
> +#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
> +#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
> +#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
> +#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
> +#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
> +#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
> +#define MT8186_DISP_OVL0_MOUT_EN 0xF18
> +#define MT8186_OVL0_MOUT_EN_MASK 0xF
> +#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
> +#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
> +#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
> +#define MT8186_DITHER0_MOUT_EN_MASK 0xF
> +#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
> +#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
> +#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
> +#define MT8186_DISP_RDMA0_SEL_IN 0xF28
> +#define MT8186_RDMA0_SEL_IN_MASK 0xF
> +#define MT8186_RDMA0_FROM_OVL0 0
> +#define MT8186_RDMA0_FROM_OVL0_2L 2
> +#define MT8186_DISP_DSI0_SEL_IN 0xF30
> +#define MT8186_DSI0_SEL_IN_MASK 0xF
> +#define MT8186_DSI0_FROM_RDMA0 0
> +#define MT8186_DSI0_FROM_DITHER0 1
> +#define MT8186_DSI0_FROM_RDMA1 2
> +#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
> +#define MT8186_RDMA1_MOUT_EN_MASK 0xF
> +#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
> +#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
> +#define MT8186_DISP_RDMA1_SEL_IN 0xF40
> +#define MT8186_RDMA1_SEL_IN_MASK 0xF
> +#define MT8186_RDMA1_FROM_OVL0 0
> +#define MT8186_RDMA1_FROM_OVL0_2L 2
> +#define MT8186_RDMA1_FROM_DITHER0 3
> +#define MT8186_DISP_DPI0_SEL_IN 0xF44
> +#define MT8186_DPI0_SEL_IN_MASK 0xF
> +#define MT8186_DPI0_FROM_RDMA1 0
> +#define MT8186_DPI0_FROM_DITHER0 1
> +#define MT8186_DPI0_FROM_RDMA0 2
> +
> +static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
> + MT8186_OVL0_MOUT_TO_RDMA0
> + },
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
> + MT8186_RDMA0_FROM_OVL0
> + },
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
> + MT8186_OVL0_GO_BLEND
> + },
> + {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
> + MT8186_RDMA0_SOUT_TO_COLOR0
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> + MT8186_DITHER0_MOUT_TO_DSI0,
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> + MT8186_DSI0_FROM_DITHER0
> + },
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
> + MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
> + MT8186_OVL0_2L_MOUT_TO_RDMA1
> + },
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
> + MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
> + MT8186_RDMA1_FROM_OVL0_2L
> + },
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
> + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
> + MT8186_OVL0_2L_GO_BLEND
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
> + MT8186_RDMA1_MOUT_TO_DPI0_SEL
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
> + MT8186_DPI0_FROM_RDMA1
> + },
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 1e448f1ffefb..0da25069ffb3 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -15,6 +15,7 @@
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> #include "mt8183-mmsys.h"
> +#include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> #include "mt8365-mmsys.h"
>
> @@ -56,6 +57,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> + .clk_driver = "clk-mt8186-mm",
> + .routes = mmsys_mt8186_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> @@ -242,6 +249,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8186-mmsys",
Add "mediatek,mt8186-mmsys" to binding document.
Regards,
Chun-Kuang.
> + .data = &mt8186_mmsys_driver_data,
> + },
> {
> .compatible = "mediatek,mt8192-mmsys",
> .data = &mt8192_mmsys_driver_data,
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH] iio: st-sensors: Update ST Sensor bindings
From: Geert Uytterhoeven @ 2022-01-28 16:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Jonathan Cameron, linux-iio, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring
In-Reply-To: <CACRpkdYGYQNQ27DD5HaUt8ERgoiNjxGE95W8EHbZRFNaXsH8VQ@mail.gmail.com>
Hi Linus,
On Fri, Jan 28, 2022 at 4:57 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Jan 28, 2022 at 4:51 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Wed, Jan 26, 2022 at 3:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Mon, Apr 12, 2021 at 2:24 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> >
> > > > interrupts:
> > > > + description: interrupt line(s) connected to the DRDY line(s) and/or the
> > > > + Intertial interrupt lines INT1 and INT2 if these exist. This means up to
> > > > + three interrupts, and the DRDY must be the first one if it exists on
> > >
> > > So this says three (the LSM9DS0 datasheet agrees)...
> > >
> > > > + the package. The trigger edge of the interrupts is sometimes software
> > > > + configurable in the hardware so the operating system should parse this
> > > > + flag and set up the trigger edge as indicated in the device tree.
> > > > minItems: 1
> > > > + maxItems: 2
> > >
> > > ... while this says two?
> >
> > Looks like a bug, could you send a patch? (I'm a bit preoccupied right now.)
>
> Oh wait a minute, LSM9DS0 is one of those with more than one component
> inside it isn't it?
Yes it is. And thus it needs 2 device nodes in DT.
> While it is a bit awkward, we do bindings per-subcomponent on these, so
> for example lsm330dlc registers as "st,lsm330dlc-accel" and "st,lsm330dlc-gyro"
> and it makes a bit of sense because they each have different I2C addresses
> as well.
>
> I see it as two components just sharing a physical package rather than one
> component in a package.
>
> So the IRQs are per-subcomponent, not for the entire package.
OK, that makes sense.
> Does this influence the situation you have with LSM9DS0?
Yes, it does. Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH V4 3/6] soc: qcom: eud: Add driver support for Embedded USB Debugger(EUD)
From: Bjorn Andersson @ 2022-01-28 16:11 UTC (permalink / raw)
To: Souradeep Chowdhury
Cc: linux-arm-msm, linux-usb, devicetree, pure.logic, greg, robh,
linux-kernel, quic_tsoni, quic_psodagud, quic_satyap,
quic_pheragu, quic_rjendra, quic_sibis, quic_saipraka
In-Reply-To: <c072d162-e371-e44b-8160-d06a8a6c051c@quicinc.com>
On Thu 27 Jan 04:01 PST 2022, Souradeep Chowdhury wrote:
>
> On 1/26/2022 10:17 AM, Bjorn Andersson wrote:
> > On Fri 21 Jan 07:53 CST 2022, Souradeep Chowdhury wrote:
[..]
> > > + return PTR_ERR(chip->base);
> > > +
> > > + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1);
> > > + if (IS_ERR(chip->mode_mgr))
> > > + return PTR_ERR(chip->mode_mgr);
> > > +
> > > + chip->irq = platform_get_irq(pdev, 0);
> > > + ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq,
> > > + handle_eud_irq_thread, IRQF_ONESHOT, NULL, chip);
> > > + if (ret)
> > > + return dev_err_probe(chip->dev, ret, "failed to allocate irq\n");
> > > +
> > > + enable_irq_wake(chip->irq);
> > > +
> > > + platform_set_drvdata(pdev, chip);
> > > +
> > > + return 0;
> > Per the updated binding, the EUD would now be a usb-role-switch as well
> > and when not enabled should simply propagate the incoming requests. So I
> > was expecting this to register as a usb_role_switch as well...
>
> Can you please elaborate on this?
>
> Do I need to define a separate 'usb_role_switch_desc' here and register
> using 'usb_role_switch_register'?
>
> Also what should be the set method in this case for usb_role_switch_desc?
>
My expectation is that in normal operation pmic_glink will provide role
switching requests and then as you enable the EUD it will force the role
to gadget.
So my suggestion was that you make eud a role-switch and as long as EUD
is disabled you just pass through the role-switch vote from pmic_glink
onto the dwc3.
Perhaps I'm misunderstanding how this is really working.
Regards,
Bjorn
^ permalink raw reply
* [PATCH 1/3] dt-bindings: interconnect: Create modified msm8939-snoc description
From: Bryan O'Donoghue @ 2022-01-28 16:10 UTC (permalink / raw)
To: djakov, bjorn.andersson, agross, linux-arm-msm, linux-pm
Cc: jun.nie, shawn.guo, benl, dmitry.baryshkov, bryan.odonoghue,
Rob Herring, devicetree
In-Reply-To: <20220128161002.2308563-1-bryan.odonoghue@linaro.org>
Subsume msm8939-snoc-mm and msm8939-snoc into the one device.
Looking at the DTS description for this downstream we see that snoc and
snoc_mm share the same address space, the same clocks, indeed the only hint
at all in qcom documentation these to are separate in anyway is boxes drawn
on a diagram.
snoc_mm is in fact simply two higher performance points for multimedia
devices tacked onto the msm8916 snoc which was reused for msm8936/msm8939.
The various client IP blocks make requests to vote for either X0 or GPLL0
clock rates with the multi-media votes indicating a higher operating point.
We don't need to model snoc and snoc_mm separately since the datasheet for
this part shows snoc_mm is not a separate device.
Breaking up snoc into two pieces is a mistake that was made downstream
which we carried over into upstream.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/interconnect/qcom,rpm.yaml | 25 +++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
index e4c3c2818119e..1110a242b2132 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
@@ -79,8 +79,6 @@ allOf:
- qcom,msm8916-snoc
- qcom,msm8939-bimc
- qcom,msm8939-pcnoc
- - qcom,msm8939-snoc
- - qcom,msm8939-snoc-mm
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
- qcom,msm8996-bimc
@@ -182,6 +180,29 @@ allOf:
- description: Aggregate2 USB3 AXI Clock.
- description: Config NoC USB2 AXI Clock.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8939-snoc
+
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: bus
+ - const: bus_a
+ - const: bus_mm
+ - const: bus_a_mm
+
+ clocks:
+ items:
+ - description: Bus Clock.
+ - description: Bus A Clock.
+ - description: Bus Clock MultiMedia.
+ - description: Bus A Clock MultiMedia.
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
--
2.33.0
^ permalink raw reply related
* [PATCH v3 12/12] arm64: dts: freescale: add initial support for verdin imx8m mini
From: Marcel Ziswiler @ 2022-01-28 16:01 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Marcel Ziswiler, Krzysztof Kozlowski, Alex Marginean,
Alexander Stein, Ariel D'Alessandro, Arnd Bergmann,
Chester Lin, Dong Aisheng, Fabio Estevam, Frank Rowand,
Jagan Teki, NXP Linux Team, Olof Johansson,
Pengutronix Kernel Team, Rob Herring, Sascha Hauer, Shawn Guo,
Tim Harvey, devicetree, linux-kernel
In-Reply-To: <20220128160100.1228537-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This patch adds the device tree to support Toradex Verdin iMX8M Mini a
computer on module which can be used on different carrier boards.
The module consists of an NXP i.MX 8M Mini family SoC (either i.MX 8M
Mini Quad or 8M Mini DualLite), a PCA9450A PMIC, a Gigabit Ethernet PHY,
1 or 2 GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an
RX8130 RTC, an optional SPI CAN controller plus an optional Bluetooth/
Wi-Fi module.
Anything that is not self-contained on the module is disabled by
default.
The device tree for the Dahlia includes the module's device tree and
enables the supported peripherals of the carrier board.
The device tree for the Verdin Development Board includes the module's
device tree as well as the Dahlia one as it is a superset and supports
almost all peripherals available.
So far there is no display functionality supported at all but basic
console UART, PCIe, USB host, eMMC and Ethernet and PCIe functionality
work fine.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Changes in v3:
- Rebase on top of shawnguo's for-next.
- Drop [PATCH v2 02/11] ("dt-bindings: gpio: fix gpio-hog example") as
it already got applied by Bart.
- Remove the 'pm-ignore-notify' property analogous to commit aafac22d6b23
("arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' property").
- Now with PCIe support finally having landed in -next enable it as well.
- Add Krzysztof's acked-by tag.
Changes in v2:
- Remove bootargs which will be filled in by the bootloader as requested
by Krzysztof.
- Remove the previously #ifdefed-out spi-nor as requested by Krzysztof.
- Fix capitalisation in cover-letter.
arch/arm64/boot/dts/freescale/Makefile | 4 +
.../dts/freescale/imx8mm-verdin-dahlia.dtsi | 150 ++
.../boot/dts/freescale/imx8mm-verdin-dev.dtsi | 67 +
.../imx8mm-verdin-nonwifi-dahlia.dts | 18 +
.../freescale/imx8mm-verdin-nonwifi-dev.dts | 18 +
.../dts/freescale/imx8mm-verdin-nonwifi.dtsi | 75 +
.../freescale/imx8mm-verdin-wifi-dahlia.dts | 18 +
.../dts/freescale/imx8mm-verdin-wifi-dev.dts | 18 +
.../dts/freescale/imx8mm-verdin-wifi.dtsi | 95 ++
.../boot/dts/freescale/imx8mm-verdin.dtsi | 1291 +++++++++++++++++
10 files changed, 1754 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 6d8f0a532587..04380f2e44a2 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -63,6 +63,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
new file mode 100644
index 000000000000..455127966e67
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/ {
+ sound_card: sound-card {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,name = "imx8mm-wm8904";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "Headphone Jack", "MICBIAS",
+ "IN1L", "Headphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Headphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ dailink_master: simple-audio-card,codec {
+ clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
+ sound-dai = <&wm8904_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+};
+
+/* Verdin SPI_1 */
+&ecspi2 {
+ status = "okay";
+};
+
+/* EEPROM on display adapter boards */
+&eeprom_display_adapter {
+ status = "okay";
+};
+
+/* EEPROM on Verdin Development board */
+&eeprom_carrier_board {
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&flexspi {
+ status = "okay";
+};
+
+/* Current measurement into module VCC */
+&hwmon {
+ status = "okay";
+};
+
+&hwmon_temp {
+ vs-supply = <®_1p8v>;
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+ status = "okay";
+
+ /* Audio Codec */
+ wm8904_1a: codec@1a {
+ compatible = "wlf,wm8904";
+ AVDD-supply = <®_3p3v>;
+ clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
+ clock-names = "mclk";
+ CPVDD-supply = <®_3p3v>;
+ DBVDD-supply = <®_3p3v>;
+ DCVDD-supply = <®_3p3v>;
+ MICVDD-supply = <®_3p3v>;
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&pwm1 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&pwm2 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&pwm3 {
+ status = "okay";
+};
+
+/* VERDIN I2S_1 */
+&sai2 {
+ status = "okay";
+};
+
+/* Verdin UART_3 */
+&uart1 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&uart2 {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&uart3 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbotg1 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbotg2 {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
new file mode 100644
index 000000000000..f35d22dc546b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+#include "imx8mm-verdin-dahlia.dtsi"
+
+/ {
+ sound_card: sound-card {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,name = "imx8mm-nau8822";
+ simple-audio-card,routing =
+ "Headphones", "LHP",
+ "Headphones", "RHP",
+ "Speaker", "LSPK",
+ "Speaker", "RSPK",
+ "Line Out", "AUXOUT1",
+ "Line Out", "AUXOUT2",
+ "LAUX", "Line In",
+ "RAUX", "Line In",
+ "LMICP", "Mic In",
+ "RMICP", "Mic In";
+ simple-audio-card,widgets =
+ "Headphones", "Headphones",
+ "Line Out", "Line Out",
+ "Speaker", "Speaker",
+ "Microphone", "Mic In",
+ "Line", "Line In";
+
+ dailink_master: simple-audio-card,codec {
+ clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
+ sound-dai = <&nau8822_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+};
+
+&gpio_expander_21 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+ /* Audio Codec */
+ nau8822_1a: codec@1a {
+ compatible = "nuvoton,nau8822";
+ reg = <0x1a>;
+ };
+};
+
+/* Verdin UART_1, connector X50 through RS485 transceiver */
+&uart2 {
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+};
+
+/* Limit frequency on dev board due to long traces and bad signal integrity */
+&usdhc2 {
+ max-frequency = <100000000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts
new file mode 100644
index 000000000000..d64ff378a152
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mm-verdin.dtsi"
+#include "imx8mm-verdin-nonwifi.dtsi"
+#include "imx8mm-verdin-dahlia.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Mini on Dahlia Board";
+ compatible = "toradex,verdin-imx8mm-nonwifi-dahlia",
+ "toradex,verdin-imx8mm-nonwifi",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts
new file mode 100644
index 000000000000..6ae71ecac8de
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mm-verdin.dtsi"
+#include "imx8mm-verdin-nonwifi.dtsi"
+#include "imx8mm-verdin-dev.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Mini on Verdin Development Board";
+ compatible = "toradex,verdin-imx8mm-nonwifi-dev",
+ "toradex,verdin-imx8mm-nonwifi",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
new file mode 100644
index 000000000000..9aff9dde1a02
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+&gpio3 {
+ gpio-line-names = "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_64",
+ "SODIMM_21",
+ "SODIMM_206",
+ "SODIMM_76",
+ "SODIMM_56",
+ "SODIMM_58",
+ "SODIMM_60",
+ "SODIMM_62",
+ "SODIMM_162",
+ "SODIMM_164",
+ "SODIMM_166",
+ "SODIMM_168",
+ "SODIMM_66",
+ "SODIMM_17",
+ "",
+ "SODIMM_156",
+ "SODIMM_160",
+ "SODIMM_244",
+ "SODIMM_250",
+ "SODIMM_48",
+ "SODIMM_44",
+ "SODIMM_42",
+ "SODIMM_46";
+};
+
+&gpio4 {
+ gpio-line-names = "SODIMM_102",
+ "SODIMM_90",
+ "SODIMM_92",
+ "SODIMM_94",
+ "SODIMM_96",
+ "SODIMM_100",
+ "SODIMM_148",
+ "SODIMM_152",
+ "SODIMM_154",
+ "SODIMM_174",
+ "SODIMM_120",
+ "SODIMM_104",
+ "SODIMM_106",
+ "SODIMM_108",
+ "SODIMM_112",
+ "SODIMM_114",
+ "SODIMM_116",
+ "SODIMM_150",
+ "SODIMM_118",
+ "",
+ "SODIMM_88",
+ "SODIMM_149",
+ "SODIMM_147",
+ "SODIMM_36",
+ "SODIMM_32",
+ "SODIMM_30",
+ "SODIMM_34",
+ "SODIMM_38",
+ "SODIMM_252",
+ "SODIMM_133",
+ "SODIMM_135",
+ "SODIMM_129";
+};
+
+&usdhc3 {
+ bus-width = <4>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts
new file mode 100644
index 000000000000..d424c475cba1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mm-verdin.dtsi"
+#include "imx8mm-verdin-wifi.dtsi"
+#include "imx8mm-verdin-dahlia.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Mini WB on Dahlia Board";
+ compatible = "toradex,verdin-imx8mm-wifi-dahlia",
+ "toradex,verdin-imx8mm-wifi",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts
new file mode 100644
index 000000000000..ef952021832e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mm-verdin.dtsi"
+#include "imx8mm-verdin-wifi.dtsi"
+#include "imx8mm-verdin-dev.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board";
+ compatible = "toradex,verdin-imx8mm-wifi-dev",
+ "toradex,verdin-imx8mm-wifi",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
new file mode 100644
index 000000000000..c400770c1df5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/ {
+ reg_wifi_en: regulator-wifi-en {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_pwr_en>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "PDn_AW-CM276NF";
+ startup-delay-us = <2000>;
+ };
+};
+
+/* On-module Wi-Fi */
+&usdhc3 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
+ vmmc-supply = <®_wifi_en>;
+ wifi-host;
+ status = "okay";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_64",
+ "SODIMM_21",
+ "SODIMM_206",
+ "SODIMM_76",
+ "SODIMM_56",
+ "SODIMM_58",
+ "SODIMM_60",
+ "SODIMM_62",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_66",
+ "SODIMM_17",
+ "",
+ "",
+ "",
+ "SODIMM_244",
+ "SODIMM_250",
+ "SODIMM_48",
+ "SODIMM_44",
+ "SODIMM_42",
+ "SODIMM_46";
+};
+
+&gpio4 {
+ gpio-line-names = "SODIMM_102",
+ "SODIMM_90",
+ "SODIMM_92",
+ "SODIMM_94",
+ "SODIMM_96",
+ "SODIMM_100",
+ "",
+ "",
+ "",
+ "SODIMM_174",
+ "SODIMM_120",
+ "SODIMM_104",
+ "SODIMM_106",
+ "SODIMM_108",
+ "SODIMM_112",
+ "SODIMM_114",
+ "SODIMM_116",
+ "",
+ "SODIMM_118",
+ "",
+ "SODIMM_88",
+ "SODIMM_149",
+ "SODIMM_147",
+ "SODIMM_36",
+ "SODIMM_32",
+ "SODIMM_30",
+ "SODIMM_34",
+ "SODIMM_38",
+ "SODIMM_252",
+ "SODIMM_133",
+ "SODIMM_135",
+ "SODIMM_129";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
new file mode 100644
index 000000000000..00df2a0f1014
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -0,0 +1,1291 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+#include "dt-bindings/phy/phy-imx8-pcie.h"
+#include "dt-bindings/pwm/pwm.h"
+#include "imx8mm.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 45 63 88 119 158 203 255>;
+ default-brightness-level = <4>;
+ /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
+ enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
+ power-supply = <®_3p3v>;
+ /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
+ pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
+ status = "disabled";
+ };
+
+ /* Fixed clock dedicated to SPI CAN controller */
+ clk20m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ debounce-interval = <10>;
+ /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
+ gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ /* Carrier Board Supplies */
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SW";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_SW";
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "+V5_SW";
+ };
+
+ /* Non PMIC On-module Supplies */
+ reg_ethphy: regulator-ethphy {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
+ off-on-delay = <500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eth>;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_ETH";
+ startup-delay-us = <200000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin USB_1_EN (SODIMM 155) */
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_otg1_vbus";
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin USB_2_EN (SODIMM 185) */
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_otg2_vbus";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin SD_1_PWR_EN (SODIMM 76) */
+ gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_SD";
+ startup-delay-us = <2000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Use the kernel configuration settings instead */
+ /delete-node/ linux,cma;
+
+ rpmsg_reserved: rpmsg@b8000000 {
+ no-map;
+ reg = <0 0xb8000000 0 0x400000>;
+ };
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+/* Verdin SPI_1 */
+&ecspi2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+};
+
+/* Verdin CAN_1 and CAN_2 (On-module) */
+&ecspi3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
+ <&gpio1 5 GPIO_ACTIVE_LOW>;
+ spi-num-chipselects = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+
+ can1: can@0 {
+ compatible = "microchip,mcp251xfd";
+ clocks = <&clk20m>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_int>;
+ reg = <0>;
+ spi-max-frequency = <8500000>;
+ };
+
+ can2: can@1 {
+ compatible = "microchip,mcp251xfd";
+ clocks = <&clk20m>;
+ interrupts-extended = <&gpio1 7 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can2_int>;
+ reg = <1>;
+ spi-max-frequency = <8500000>;
+ /* Not assembled on regular SKUs */
+ status = "disabled";
+ };
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&fec1 {
+ fsl,magic-packet;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ phy-supply = <®_ethphy>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <&gpio1>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/* Verdin QSPI_1 */
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+};
+
+&gpio1 {
+ gpio-line-names = "SODIMM_216",
+ "SODIMM_19",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_220",
+ "SODIMM_222",
+ "",
+ "SODIMM_218",
+ "SODIMM_155",
+ "SODIMM_157",
+ "SODIMM_185",
+ "SODIMM_187";
+};
+
+&gpio2 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_84",
+ "SODIMM_78",
+ "SODIMM_74",
+ "SODIMM_80",
+ "SODIMM_82",
+ "SODIMM_70",
+ "SODIMM_72";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_131",
+ "",
+ "SODIMM_91",
+ "SODIMM_16",
+ "SODIMM_15",
+ "SODIMM_208",
+ "SODIMM_137",
+ "SODIMM_139",
+ "SODIMM_141",
+ "SODIMM_143",
+ "SODIMM_196",
+ "SODIMM_200",
+ "SODIMM_198",
+ "SODIMM_202",
+ "",
+ "",
+ "SODIMM_55",
+ "SODIMM_53",
+ "SODIMM_95",
+ "SODIMM_93",
+ "SODIMM_14",
+ "SODIMM_12",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_210",
+ "SODIMM_212",
+ "SODIMM_151",
+ "SODIMM_153";
+
+ ctrl_sleep_moci-hog {
+ gpio-hog;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ line-name = "CTRL_SLEEP_MOCI#";
+ output-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+ };
+};
+
+/* On-module I2C */
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450a";
+ interrupt-parent = <&gpio1>;
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x25>;
+ sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ nxp,dvs-run-voltage = <850000>;
+ nxp,dvs-standby-voltage = <800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <800000>;
+ regulator-name = "+VDD_SOC";
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "+VDD_ARM";
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_vdd_dram: BUCK3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "+VDD_GPU_VPU_DDR";
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3";
+ };
+
+ reg_vdd_1v8: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "PWR_1V8_MOCI";
+ };
+
+ reg_nvcc_dram: BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "+VDD_DDR";
+ };
+
+ reg_nvcc_snvs: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SNVS";
+ };
+
+ reg_vdd_snvs: LDO2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <800000>;
+ regulator-name = "+V0.8_SNVS";
+ };
+
+ reg_vdda: LDO3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8A";
+ };
+
+ reg_vdd_phy: LDO4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <900000>;
+ regulator-name = "+V0.9_MIPI";
+ };
+
+ reg_nvcc_sd: LDO5 {
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V3.3_1.8_SD";
+ };
+ };
+ };
+
+ rtc_i2c: rtc@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Verdin I2C_1 (ADC_4 - ADC_3) */
+ channel@0 {
+ reg = <0>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 (ADC_4 - ADC_1) */
+ channel@1 {
+ reg = <1>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 (ADC_3 - ADC_1) */
+ channel@2 {
+ reg = <2>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 (ADC_2 - ADC_1) */
+ channel@3 {
+ reg = <3>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 ADC_4 */
+ channel@4 {
+ reg = <4>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 ADC_3 */
+ channel@5 {
+ reg = <5>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 ADC_2 */
+ channel@6 {
+ reg = <6>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+
+ /* Verdin I2C_1 ADC_1 */
+ channel@7 {
+ reg = <7>;
+ ti,datarate = <4>;
+ ti,gain = <2>;
+ };
+ };
+
+ eeprom@50 {
+ compatible = "st,24c02";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
+
+/* Verdin I2C_2_DSI */
+&i2c2 {
+ clock-frequency = <10000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "disabled";
+};
+
+/* Verdin I2C_3_HDMI N/A */
+
+/* Verdin I2C_4_CSI */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ gpio_expander_21: gpio-expander@21 {
+ compatible = "nxp,pcal6416";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x21>;
+ status = "disabled";
+ vcc-supply = <®_3p3v>;
+ };
+
+ lvds_ti_sn65dsi83: bridge@2c {
+ compatible = "ti,sn65dsi83";
+ /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
+ /* Verdin GPIO_10_DSI (SODIMM 21) */
+ enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_10_dsi>;
+ reg = <0x2c>;
+ status = "disabled";
+ };
+
+ /* Current measurement into module VCC */
+ hwmon: hwmon@40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ status = "disabled";
+ };
+
+ hdmi_lontium_lt8912: hdmi@48 {
+ compatible = "lontium,lt8912b";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
+ reg = <0x48>;
+ /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
+ /* Verdin GPIO_10_DSI (SODIMM 21) */
+ reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+ };
+
+ atmel_mxt_ts: touch@4a {
+ compatible = "atmel,maxtouch";
+ /* Verdin GPIO_9_DSI */
+ /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */
+ interrupt-parent = <&gpio3>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
+ reg = <0x4a>;
+ /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
+ reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ /* Temperature sensor on carrier board */
+ hwmon_temp: sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ status = "disabled";
+ };
+
+ /* EEPROM on display adapter (MIPI DSI Display Adapter) */
+ eeprom_display_adapter: eeprom@50 {
+ compatible = "st,24c02";
+ pagesize = <16>;
+ reg = <0x50>;
+ status = "disabled";
+ };
+
+ /* EEPROM on carrier board */
+ eeprom_carrier_board: eeprom@57 {
+ compatible = "st,24c02";
+ pagesize = <16>;
+ reg = <0x57>;
+ status = "disabled";
+ };
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ /* PCIE_1_RESET# (SODIMM 244) */
+ reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie_phy {
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+};
+
+/* Verdin PWM_3_DSI */
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_1>;
+ #pwm-cells = <3>;
+};
+
+/* Verdin PWM_1 */
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_2>;
+ #pwm-cells = <3>;
+};
+
+/* Verdin PWM_2 */
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_3>;
+ #pwm-cells = <3>;
+};
+
+/* VERDIN I2S_1 */
+&sai2 {
+ #sound-dai-cells = <0>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* Verdin UART_3, used as the Linux console */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+/* Verdin UART_1 */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+};
+
+/* Verdin UART_2 */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+};
+
+/* Verdin UART_4 */
+/*
+ * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
+ */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+};
+
+&usbmisc1 {
+ vbus-wakeup-supply = <®_vdd_3v3>;
+};
+
+&usbmisc2 {
+ vbus-wakeup-supply = <®_vdd_3v3>;
+};
+
+/* Verdin USB_1 */
+&usbotg1 {
+ adp-disable;
+ dr_mode = "otg";
+ hnp-disable;
+ over-current-active-low;
+ picophy,dc-vol-level-adjust = <7>;
+ picophy,pre-emp-curr-control = <3>;
+ srp-disable;
+ vbus-supply = <®_usb_otg1_vbus>;
+};
+
+/* Verdin USB_2 */
+&usbotg2 {
+ dr_mode = "host";
+ over-current-active-low;
+ picophy,dc-vol-level-adjust = <7>;
+ picophy,pre-emp-curr-control = <3>;
+ vbus-supply = <®_usb_otg2_vbus>;
+};
+
+&usbphynop1 {
+ vcc-supply = <®_vdd_3v3>;
+};
+
+&usbphynop2 {
+ vcc-supply = <®_vdd_3v3>;
+};
+
+/* On-module eMMC */
+&usdhc1 {
+ bus-width = <8>;
+ keep-power-in-suspend;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+};
+
+&wdog1 {
+ fsl,ext-reset-output;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
+ <&pinctrl_gpio3>, <&pinctrl_gpio4>,
+ <&pinctrl_gpio7>, <&pinctrl_gpio8>,
+ <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
+ <&pinctrl_pmic_tpm_ena>;
+
+ pinctrl_can1_int: can1intgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4>; /* CAN_1_SPI_INT#_1.8V */
+ };
+
+ pinctrl_can2_int: can2intgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4>; /* CAN_2_SPI_INT#_1.8V */
+ };
+
+ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4>; /* SODIMM 256 */
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4>, /* SODIMM 196 */
+ <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4>, /* SODIMM 200 */
+ <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4>, /* SODIMM 198 */
+ <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4>; /* SODIMM 202 */
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4>, /* CAN_SPI_SCK_1.8V */
+ <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4>, /* CAN_SPI_MOSI_1.8V */
+ <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4>, /* CAN_SPI_MISO_1.8V */
+ <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4>, /* CAN_1_SPI_CS_1.8V# */
+ <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4>; /* CAN_2_SPI_CS#_1.8V */
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
+ <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
+ <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
+ <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
+ <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
+ <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
+ <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
+ <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
+ <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
+ <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
+ <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
+ <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4>;
+ };
+
+ pinctrl_fec1_sleep: fec1-sleepgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
+ <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
+ <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
+ <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
+ <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
+ <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
+ <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
+ <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
+ <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
+ <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
+ <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
+ <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184>;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
+ <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, /* SODIMM 54 */
+ <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82>, /* SODIMM 64 */
+ <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82>, /* SODIMM 66 */
+ <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, /* SODIMM 56 */
+ <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, /* SODIMM 58 */
+ <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, /* SODIMM 60 */
+ <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; /* SODIMM 62 */
+ };
+
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184>; /* SODIMM 206 */
+ };
+
+ pinctrl_gpio2: gpio2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4>; /* SODIMM 208 */
+ };
+
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184>; /* SODIMM 210 */
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184>; /* SODIMM 212 */
+ };
+
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184>; /* SODIMM 216 */
+ };
+
+ pinctrl_gpio6: gpio6grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184>; /* SODIMM 218 */
+ };
+
+ pinctrl_gpio7: gpio7grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184>; /* SODIMM 220 */
+ };
+
+ pinctrl_gpio8: gpio8grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184>; /* SODIMM 222 */
+ };
+
+ /* Verdin GPIO_9_DSI (pulled-up as active-low) */
+ pinctrl_gpio_9_dsi: gpio9dsigrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4>; /* SODIMM 17 */
+ };
+
+ /* Verdin GPIO_10_DSI */
+ pinctrl_gpio_10_dsi: gpio10dsigrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4>; /* SODIMM 21 */
+ };
+
+ pinctrl_gpio_hog1: gpiohog1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4>, /* SODIMM 88 */
+ <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4>, /* SODIMM 90 */
+ <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4>, /* SODIMM 92 */
+ <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4>, /* SODIMM 94 */
+ <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4>, /* SODIMM 96 */
+ <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4>, /* SODIMM 100 */
+ <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4>, /* SODIMM 102 */
+ <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4>, /* SODIMM 104 */
+ <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4>, /* SODIMM 106 */
+ <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4>, /* SODIMM 108 */
+ <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4>, /* SODIMM 112 */
+ <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4>, /* SODIMM 114 */
+ <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4>, /* SODIMM 116 */
+ <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4>, /* SODIMM 118 */
+ <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4>; /* SODIMM 120 */
+ };
+
+ pinctrl_gpio_hog2: gpiohog2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4>; /* SODIMM 91 */
+ };
+
+ pinctrl_gpio_hog3: gpiohog3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4>, /* SODIMM 157 */
+ <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4>; /* SODIMM 187 */
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4>; /* SODIMM 252 */
+ };
+
+ /* On-module I2C */
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
+ <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
+ <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
+ };
+
+ /* Verdin I2C_4_CSI */
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6>, /* SODIMM 55 */
+ <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6>; /* SODIMM 53 */
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
+ <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
+ };
+
+ /* Verdin I2C_2_DSI */
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6>, /* SODIMM 95 */
+ <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6>; /* SODIMM 93 */
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
+ <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
+ };
+
+ /* Verdin I2C_1 */
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6>, /* SODIMM 14 */
+ <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6>; /* SODIMM 12 */
+ };
+
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
+ <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
+ };
+
+ /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
+ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x184>; /* SODIMM 42 */
+ };
+
+ /* Verdin I2S_2_D_OUT shared with SAI5 */
+ pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x184>; /* SODIMM 46 */
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
+ /* PMIC_EN_PCIe_CLK, unused */
+ <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
+ };
+
+ pinctrl_pmic: pmicirqgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41>; /* PMIC_INT# */
+ };
+
+ /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
+ pinctrl_pwm_1: pwm1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
+ };
+
+ pinctrl_pwm_2: pwm2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
+ };
+
+ pinctrl_pwm_3: pwm3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
+ };
+
+ /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
+ pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x184>; /* SODIMM 19 */
+ };
+
+ pinctrl_reg_eth: regethgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
+ };
+
+ pinctrl_reg_usb1_en: regusb1engrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184>; /* SODIMM 155 */
+ };
+
+ pinctrl_reg_usb2_en: regusb2engrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184>; /* SODIMM 185 */
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6>, /* SODIMM 32 */
+ <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6>, /* SODIMM 30 */
+ <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6>, /* SODIMM 38 */
+ <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6>, /* SODIMM 36 */
+ <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6>; /* SODIMM 34 */
+ };
+
+ pinctrl_sai5: sai5grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6>, /* SODIMM 48 */
+ <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6>, /* SODIMM 44 */
+ <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6>, /* SODIMM 42 */
+ <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6>; /* SODIMM 46 */
+ };
+
+ /* control signal for optional ATTPM20P or SE050 */
+ pinctrl_pmic_tpm_ena: pmictpmenagrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4>; /* PMIC_TPM_ENA */
+ };
+
+ pinctrl_tsp: tspgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140>, /* SODIMM 148 */
+ <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140>, /* SODIMM 152 */
+ <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140>, /* SODIMM 154 */
+ <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140>, /* SODIMM 179 */
+ <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140>; /* SODIMM 150 */
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4>, /* SODIMM 149 */
+ <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4>; /* SODIMM 147 */
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4>, /* SODIMM 129 */
+ <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4>, /* SODIMM 131 */
+ <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4>, /* SODIMM 133 */
+ <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4>; /* SODIMM 135 */
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4>, /* SODIMM 137 */
+ <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4>, /* SODIMM 139 */
+ <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4>, /* SODIMM 141 */
+ <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4>; /* SODIMM 143 */
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
+ <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
+ <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
+ <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
+ <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
+ <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
+ <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
+ <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
+ <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
+ <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
+ <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
+ <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
+ <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
+ <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
+ };
+
+ pinctrl_usdhc2_cd: usdhc2cdgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4>; /* SODIMM 84 */
+ };
+
+ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184>; /* SODIMM 76 */
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190>, /* SODIMM 78 */
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0>, /* SODIMM 74 */
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0>, /* SODIMM 72 */
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194>,
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196>,
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6>,
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6>,
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6>,
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6>,
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6>,
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
+ };
+
+ /* On-module Wi-Fi/BT or type specific SDHC interface */
+ /* (e.g. on X52 extension slot of Verdin Development Board) */
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0>,
+ <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0>,
+ <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0>,
+ <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0>,
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0>;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4>,
+ <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
+ <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
+ <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6>,
+ <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6>,
+ <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6>,
+ <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6>,
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6>;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
+ };
+
+ pinctrl_wifi_ctrl: wifictrlgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4>, /* WIFI_WKUP_BT */
+ <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4>, /* WIFI_W_WKUP_HOST */
+ <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4>; /* WIFI_WKUP_WLAN */
+ };
+
+ pinctrl_wifi_i2s: bti2sgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6>, /* WIFI_TX_BCLK */
+ <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6>, /* WIFI_TX_DATA0 */
+ <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6>, /* WIFI_TX_SYNC */
+ <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6>; /* WIFI_RX_DATA0 */
+ };
+
+ pinctrl_wifi_pwr_en: wifipwrengrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184>; /* PMIC_EN_WIFI */
+ };
+};
--
2.33.1
^ permalink raw reply related
* [PATCH v3 11/12] dt-bindings: arm: fsl: add toradex,verdin-imx8mm et al.
From: Marcel Ziswiler @ 2022-01-28 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Marcel Ziswiler, Rob Herring, Alexander Stein,
Christoph Niedermaier, Frank Rowand, Jagan Teki,
Krzysztof Kozlowski, Li Yang, Lucas Stach, Matthias Schiffer,
Oleksij Rempel, Rob Herring, Russell King, Sascha Hauer,
Shawn Guo, devicetree, linux-kernel
In-Reply-To: <20220128160100.1228537-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add toradex,verdin-imx8mm for our new Verdin iMX8M Mini modules, its
nonwifi and wifi variants and the carrier boards (both Dahlia and the
Verdin Development Board) they may be mated in.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Rob Herring <robh@kernel.org>
---
(no changes since v2)
Changes in v2:
- Add Rob's acked-by tag.
- Fix Colibri vs. Verdin copy/paste mistake. Thanks to Francesco Dolcini
<francesco.dolcini@toradex.com> for pointing that out to me.
.../devicetree/bindings/arm/fsl.yaml | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 5075fd8c1b42..4ddeb9b20195 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -770,6 +770,9 @@ properties:
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
+ - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
+ - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
+ - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
@@ -788,6 +791,24 @@ properties:
- const: kontron,imx8mm-n801x-som
- const: fsl,imx8mm
+ - description: Toradex Boards with Verdin iMX8M Mini Modules
+ items:
+ - enum:
+ - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
+ - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
+ - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
+ - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
+ - const: fsl,imx8mm
+
+ - description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules
+ items:
+ - enum:
+ - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
+ - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
+ - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
+ - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
+ - const: fsl,imx8mm
+
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
--
2.33.1
^ permalink raw reply related
* [PATCH v3 00/12] arm64: prepare and add verdin imx8m mini support
From: Marcel Ziswiler @ 2022-01-28 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Marcel Ziswiler, Alex Marginean, Alexander Stein,
Alexei Starovoitov, Andrii Nakryiko, Ariel D'Alessandro,
Arnd Bergmann, Biju Das, Bjorn Andersson, Catalin Marinas,
Chester Lin, Christoph Niedermaier, Daniel Borkmann, Dong Aisheng,
Enric Balletbo i Serra, Fabio Estevam, Frank Rowand,
Geert Uytterhoeven, Jagan Teki, John Fastabend, KP Singh,
Krzysztof Kozlowski, Krzysztof Kozlowski, Li Yang, Lucas Stach,
Martin KaFai Lau, Matthias Schiffer, NXP Linux Team,
Oleksij Rempel, Oliver Stäbler, Olof Johansson,
Pengutronix Kernel Team, Rob Herring, Russell King, Sascha Hauer,
Shawn Guo, Song Liu, Tim Harvey, Will Deacon, Yonghong Song, bpf,
devicetree, linux-kernel, netdev
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Fix strange hex notation and gpio-hog example, rebuild default
configuration, enable various relevant configuration options mainly to
be built as modules, add toradex,verdin-imx8mm et al. to dt-bindings and
finally, add initial support for Verdin iMX8M Mini.
Changes in v3:
- Rebase on top of shawnguo's for-next.
- Drop [PATCH v2 02/11] ("dt-bindings: gpio: fix gpio-hog example") as
it already got applied by Bart.
- Add Krzysztof's reviewed-by tag.
- New separate patch only for re-ordering as suggested by Krzysztof.
- Not dropping CONFIG_SECCOMP=y, CONFIG_SLIMBUS=m, CONFIG_INTERCONNECT=y
and CONFIG_CONFIGFS_FS=y as requested by Krzysztof.
- New patch enabling imx8m pcie phy driver in arm64 defconfig.
- Remove the 'pm-ignore-notify' property analogous to commit aafac22d6b23
("arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' property").
- Now with PCIe support finally having landed in -next enable it as well.
- Add Krzysztof's acked-by tag.
Changes in v2:
- Add Laurent's reviewed-by tag.
- New patch following full defconfig analysis as requested by Krzysztof.
- New patch following full defconfig analysis as requested by Krzysztof.
- Done full defconfig analysis as requested by Krzysztof.
- Add Song's acked-by tag.
- A similar change got accepted for imx_v6_v7_defconfig. Further
discussion may be found in [1].
[1] https://lore.kernel.org/lkml/20210920144938.314588-6-marcel@ziswiler.com/
- Explain why enabling it may be a good idea as requested by Krzysztof.
- Explain why enabling these may make sense and squash them relevant
changes as requested by Krzysztof.
- Add Rob's acked-by tag.
- Fix Colibri vs. Verdin copy/paste mistake. Thanks to Francesco Dolcini
<francesco.dolcini@toradex.com> for pointing that out to me.
- Remove bootargs which will be filled in by the bootloader as requested
by Krzysztof.
- Remove the previously #ifdefed-out spi-nor as requested by Krzysztof.
- Fix capitalisation in cover-letter.
Marcel Ziswiler (12):
arm64: dts: imx8mm: fix strange hex notation
arm64: defconfig: enable taskstats configuration
arm64: defconfig: enable pcieaer configuration
arm64: defconfig: re-order default configuration
arm64: defconfig: rebuild default configuration
arm64: defconfig: enable bpf/cgroup firewalling
arm64: defconfig: enable imx8m pcie phy driver
arm64: defconfig: build imx-sdma as a module
arm64: defconfig: build r8169 as a module
arm64: defconfig: enable verdin-imx8mm relevant drivers as modules
dt-bindings: arm: fsl: add toradex,verdin-imx8mm et al.
arm64: dts: freescale: add initial support for verdin imx8m mini
.../devicetree/bindings/arm/fsl.yaml | 21 +
arch/arm64/boot/dts/freescale/Makefile | 4 +
.../arm64/boot/dts/freescale/imx8mm-pinfunc.h | 6 +-
.../dts/freescale/imx8mm-verdin-dahlia.dtsi | 150 ++
.../boot/dts/freescale/imx8mm-verdin-dev.dtsi | 67 +
.../imx8mm-verdin-nonwifi-dahlia.dts | 18 +
.../freescale/imx8mm-verdin-nonwifi-dev.dts | 18 +
.../dts/freescale/imx8mm-verdin-nonwifi.dtsi | 75 +
.../freescale/imx8mm-verdin-wifi-dahlia.dts | 18 +
.../dts/freescale/imx8mm-verdin-wifi-dev.dts | 18 +
.../dts/freescale/imx8mm-verdin-wifi.dtsi | 95 ++
.../boot/dts/freescale/imx8mm-verdin.dtsi | 1291 +++++++++++++++++
arch/arm64/configs/defconfig | 126 +-
13 files changed, 1839 insertions(+), 68 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
--
2.33.1
^ permalink raw reply
* [PATCH v3 01/12] arm64: dts: imx8mm: fix strange hex notation
From: Marcel Ziswiler @ 2022-01-28 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Marcel Ziswiler, Laurent Pinchart, Arnd Bergmann,
Fabio Estevam, Frank Rowand, NXP Linux Team, Oliver Stäbler,
Olof Johansson, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, linux-kernel
In-Reply-To: <20220128160100.1228537-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Fix strange hex notation with mixed lower-case and upper-case letters.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
(no changes since v2)
Changes in v2:
- Add Laurent's reviewed-by tag.
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
index a003e6af3353..c68a5e456025 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
+++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
@@ -279,7 +279,7 @@
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
-#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
@@ -486,7 +486,7 @@
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
-#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
@@ -494,7 +494,7 @@
#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
-#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3
+#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3
#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
--
2.33.1
^ permalink raw reply related
* Re: [PATCH] spi: dt-bindings: Fix 'reg' child node schema
From: Mark Brown @ 2022-01-28 15:59 UTC (permalink / raw)
To: Rob Herring, Pratyush Yadav; +Cc: devicetree, linux-kernel, linux-spi
In-Reply-To: <20220126231326.1636199-1-robh@kernel.org>
On Wed, 26 Jan 2022 17:13:26 -0600, Rob Herring wrote:
> The schema for SPI child nodes' 'reg' property is not complete. 'reg' is
> a matrix of cells. The schema needs to define both the number of 'reg'
> entries and constraints on each entry.
>
>
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-linus
Thanks!
[1/1] spi: dt-bindings: Fix 'reg' child node schema
commit: 60b1e97140a487608b7cbde774b3cff1b5a99c00
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH] dt-bindings: regulator: maxim,max8973: Drop Tegra specifics from example
From: Mark Brown @ 2022-01-28 15:58 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Liam Girdwood; +Cc: linux-kernel, devicetree
In-Reply-To: <20220126231250.1635021-1-robh@kernel.org>
On Wed, 26 Jan 2022 17:12:50 -0600, Rob Herring wrote:
> There's no need to complicate examples with a platform specific macro.
> It also complicates example parsing to figure out the number of interrupt
> cells in examples (based on the bracketing).
>
>
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-next
Thanks!
[1/1] dt-bindings: regulator: maxim,max8973: Drop Tegra specifics from example
commit: fa183433bf53ee092323005f05cb3491e4aaaa8b
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: (subset) [PATCH v3 0/5] Tegra234 APE support
From: Mark Brown @ 2022-01-28 15:58 UTC (permalink / raw)
To: tiwai, lgirdwood, thierry.reding, perex, Sameer Pujar, robh+dt
Cc: jonathanh, alsa-devel, linux-kernel, devicetree, mkumard,
linux-tegra
In-Reply-To: <1643373476-8538-1-git-send-email-spujar@nvidia.com>
On Fri, 28 Jan 2022 18:07:51 +0530, Sameer Pujar wrote:
> This adds APE support on Tegra234 and enables sound card on
> Jetson AGX Orin platform.
>
>
> Changelog
> =========
> v2->v3
> ------
> * Fixed DT build error related to power-domain and
> iommu reference.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/5] ASoC: tegra: Update AHUB driver for Tegra234
commit: 4fcc8710fdd91b37760ccd99bbfbe10352df7600
[3/5] dt-bindings: Document Tegra234 APE support
commit: fed44d6c3bcdb11ed77bc681f1cf80cbe8cfd9a5
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: (subset) [PATCH v2 0/5] Tegra234 APE support
From: Mark Brown @ 2022-01-28 15:58 UTC (permalink / raw)
To: tiwai, lgirdwood, thierry.reding, perex, Sameer Pujar, robh+dt
Cc: jonathanh, linux-kernel, alsa-devel, devicetree, mkumard,
linux-tegra
In-Reply-To: <1643268455-15567-1-git-send-email-spujar@nvidia.com>
On Thu, 27 Jan 2022 12:57:30 +0530, Sameer Pujar wrote:
> This adds APE support on Tegra234 and enables sound card on
> Jetson AGX Orin platform.
>
>
> Changelog
> =========
> v1->v2
> ------
> * Rebased patches on latest linux-next
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/5] ASoC: tegra: Update AHUB driver for Tegra234
commit: 4fcc8710fdd91b37760ccd99bbfbe10352df7600
[3/5] dt-bindings: Document Tegra234 APE support
(no commit info)
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH] ASoC: dt-bindings: realtek,rt5682s: Drop Tegra specifics from example
From: Mark Brown @ 2022-01-28 15:58 UTC (permalink / raw)
To: Liam Girdwood, Rob Herring, Derek Fang
Cc: linux-kernel, alsa-devel, devicetree
In-Reply-To: <20220126231358.1637174-1-robh@kernel.org>
On Wed, 26 Jan 2022 17:13:58 -0600, Rob Herring wrote:
> There's no need to complicate examples with a platform specific macro.
> It also complicates example parsing to figure out the number of interrupt
> cells in examples (based on bracketing).
>
>
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] ASoC: dt-bindings: realtek,rt5682s: Drop Tegra specifics from example
commit: 0cfe76156cc1c7f8a707969c03ed2242db8f0292
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH] iio: st-sensors: Update ST Sensor bindings
From: Linus Walleij @ 2022-01-28 15:57 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jonathan Cameron, linux-iio, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring
In-Reply-To: <CACRpkdbrX-JiPJh2pnVPt39mNgNNrAFkOfS8Q9kO002+oVagyg@mail.gmail.com>
On Fri, Jan 28, 2022 at 4:51 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Wed, Jan 26, 2022 at 3:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, Apr 12, 2021 at 2:24 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> > > interrupts:
> > > + description: interrupt line(s) connected to the DRDY line(s) and/or the
> > > + Intertial interrupt lines INT1 and INT2 if these exist. This means up to
> > > + three interrupts, and the DRDY must be the first one if it exists on
> >
> > So this says three (the LSM9DS0 datasheet agrees)...
> >
> > > + the package. The trigger edge of the interrupts is sometimes software
> > > + configurable in the hardware so the operating system should parse this
> > > + flag and set up the trigger edge as indicated in the device tree.
> > > minItems: 1
> > > + maxItems: 2
> >
> > ... while this says two?
>
> Looks like a bug, could you send a patch? (I'm a bit preoccupied right now.)
Oh wait a minute, LSM9DS0 is one of those with more than one component
inside it isn't it?
While it is a bit awkward, we do bindings per-subcomponent on these, so
for example lsm330dlc registers as "st,lsm330dlc-accel" and "st,lsm330dlc-gyro"
and it makes a bit of sense because they each have different I2C addresses
as well.
I see it as two components just sharing a physical package rather than one
component in a package.
So the IRQs are per-subcomponent, not for the entire package.
Does this influence the situation you have with LSM9DS0?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] iio: st-sensors: Update ST Sensor bindings
From: Linus Walleij @ 2022-01-28 15:51 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jonathan Cameron, linux-iio, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring
In-Reply-To: <CAMuHMdUYOxKECcF+aM3+pTpgp-412YbL5vMDZpmEqJmLigpdVw@mail.gmail.com>
On Wed, Jan 26, 2022 at 3:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Apr 12, 2021 at 2:24 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > interrupts:
> > + description: interrupt line(s) connected to the DRDY line(s) and/or the
> > + Intertial interrupt lines INT1 and INT2 if these exist. This means up to
> > + three interrupts, and the DRDY must be the first one if it exists on
>
> So this says three (the LSM9DS0 datasheet agrees)...
>
> > + the package. The trigger edge of the interrupts is sometimes software
> > + configurable in the hardware so the operating system should parse this
> > + flag and set up the trigger edge as indicated in the device tree.
> > minItems: 1
> > + maxItems: 2
>
> ... while this says two?
Looks like a bug, could you send a patch? (I'm a bit preoccupied right now.)
Thanks!
Linus Walleij
^ permalink raw reply
* Re: [PATCH net-next v2 9/9] net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs
From: Jakub Kicinski @ 2022-01-28 15:44 UTC (permalink / raw)
To: Biao Huang
Cc: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Yinghua Pan, srv_heupstream,
Macpaul Lin
In-Reply-To: <2bdb6c9b5ec90b6c606b7db8c13f8acb34910b36.camel@mediatek.com>
On Fri, 28 Jan 2022 15:05:27 +0800 Biao Huang wrote:
> > > + * Description : this is the driver interrupt service routine.
> > > + * it mainly handles:
> > > + * 1. tx complete interrupt for frame transmission.
> > > + * 2. rx complete interrupt for frame reception.
> > > + * 3. MAC Management Counter interrupt to avoid counter overflow.
> > > */
> > > static irqreturn_t mtk_star_handle_irq(int irq, void *data)
> > > {
> > > - struct mtk_star_priv *priv;
> > > - struct net_device *ndev;
> > > + struct net_device *ndev = data;
> > > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > > + unsigned int intr_status = mtk_star_intr_ack_all(priv);
> > > + unsigned long flags = 0;
> > > +
> > > + if (intr_status & MTK_STAR_BIT_INT_STS_FNRC) {
> > > + if (napi_schedule_prep(&priv->rx_napi)) {
> > > + spin_lock_irqsave(&priv->lock, flags);
> > > + /* mask Rx Complete interrupt */
> > > + mtk_star_disable_dma_irq(priv, true, false);
> > > + spin_unlock_irqrestore(&priv->lock, flags);
> > > + __napi_schedule_irqoff(&priv->rx_napi);
> > > + }
> > > + }
> > >
> > > - ndev = data;
> > > - priv = netdev_priv(ndev);
> > > + if (intr_status & MTK_STAR_BIT_INT_STS_TNTC) {
> > > + if (napi_schedule_prep(&priv->tx_napi)) {
> > > + spin_lock_irqsave(&priv->lock, flags);
> > > + /* mask Tx Complete interrupt */
> > > + mtk_star_disable_dma_irq(priv, false, true);
> > > + spin_unlock_irqrestore(&priv->lock, flags);
> > > + __napi_schedule_irqoff(&priv->tx_napi);
> > > + }
> > > + }
> >
> > Seems a little wasteful to retake the same lock twice if two IRQ
> > sources fire at the same time.
> The TX/RX irq control bits are in the same register,
> but they are triggered independently.
> So it seems necessary to protect the register
> access with a spin lock.
This is what I meant:
rx = (status & RX) && napi_schedule_prep(rx_napi);
tx = (status & TX) && napi_schedule_prep(tx_napi);
if (rx || tx) {
spin_lock()
disable_irq(priv, rx, tx);
spin_unlock();
if (rx)
__napi_schedule_irqoff(rx_napi)
if (tx)
__napi_schedule_irqoff(tx_napi)
}
> > > desc_data.dma_addr = mtk_star_dma_map_tx(priv, skb);
> > > if (dma_mapping_error(dev, desc_data.dma_addr))
> > > @@ -1050,18 +1103,10 @@ static int
> > > mtk_star_netdev_start_xmit(struct sk_buff *skb,
> > >
> > > desc_data.skb = skb;
> > > desc_data.len = skb->len;
> > > -
> > > - spin_lock_bh(&priv->lock);
> > >
> > > mtk_star_ring_push_head_tx(ring, &desc_data);
> > >
> > > netdev_sent_queue(ndev, skb->len);
> > >
> > > - if (mtk_star_ring_full(ring))
> > > - netif_stop_queue(ndev);
> >
> > Are you stopping the queue in advance somewhere else now? Did you
> > only
> > test this with BQL enabled? Only place that stops the ring also
> > prints
> > a loud warning now AFAICS..
> No.
>
> We modify the ring full condition, and will not invoke netif_stop_queue
> if queue is already stopped.
I don't understand what you're saying.
> Test pass no matter whether BQL is enabled or disabled.
>
> It's much safer to judge queue is full or not at the beginning of
> start_xmit() to avoid invalid setting.
Drivers are expected to stop their queues at the end of xmit routine if
the ring can't accommodate another frame. It's more efficient to stop
the queues early than have to put skbs already dequeued from the qdisc
layer back into the qdiscs.
^ permalink raw reply
* Re: [PATCH] of/fdt: move elfcorehdr reservation early for crash dump kernel
From: Rob Herring @ 2022-01-28 15:32 UTC (permalink / raw)
To: nikhil.gupta
Cc: linux-arm-kernel, Frank Rowand, devicetree,
linux-kernel@vger.kernel.org, Priyanka Jain, Dong Aisheng
In-Reply-To: <20220128042321.15228-1-nikhil.gupta@nxp.com>
On Thu, Jan 27, 2022 at 10:23 PM <nikhil.gupta@nxp.com> wrote:
>
> From: Nikhil Gupta <nikhil.gupta@nxp.com>
>
> elfcorehdr_addr is fixed address passed to Second kernel which may be conflicted
> with potential reserved memory in Second kernel,so fdt_reserve_elfcorehdr() ahead
> of fdt_init_reserved_mem() can relieve this situation.
How does changing the order help exactly? If you have an overlap, that
seems bad no matter what. What if the overlapping reserved area is
used by another core or firmware?
Rob
^ permalink raw reply
* Re: [PATCH net-next v4 0/2] Allow disabling KSZ switch refclock
From: patchwork-bot+netdevbpf @ 2022-01-28 15:10 UTC (permalink / raw)
To: Robert Hancock
Cc: netdev, woojung.huh, UNGLinuxDriver, andrew, vivien.didelot,
f.fainelli, olteanv, davem, kuba, robh+dt, marex, devicetree
In-Reply-To: <20220127164156.3677856-1-robert.hancock@calian.com>
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Thu, 27 Jan 2022 10:41:54 -0600 you wrote:
> The reference clock output from the KSZ9477 and related Microchip
> switch devices is not required on all board designs. Add a device
> tree property to disable it for power and EMI reasons.
>
> Changes since v3:
> -rework some code for simplicity
>
> [...]
Here is the summary with links:
- [net-next,v4,1/2] net: dsa: microchip: Document property to disable reference clock
https://git.kernel.org/netdev/net-next/c/eccfecfe587b
- [net-next,v4,2/2] net: dsa: microchip: Add property to disable reference clock
https://git.kernel.org/netdev/net-next/c/48bf8b8a04c9
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8150: Add ufs power-domain entries
From: Alexey Minnekhanov @ 2022-01-28 14:07 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm
Cc: bhupesh.linux, linux-kernel, devicetree, robh+dt, bjorn.andersson,
agross, Rob Herring
In-Reply-To: <20220120082803.15535-1-bhupesh.sharma@linaro.org>
At 20.01.2022 11:28, Bhupesh Sharma wrote:
> Add power-domain entries for UFS controller & phy nodes
> in sm8150 dts.
>
> ...
> + power-domains = <&gcc UFS_PHY_GDSC>;
> resets = <&gcc GCC_UFS_PHY_BCR>;
> reset-names = "rst";
> ...
> + power-domains = <&gcc UFS_CARD_GDSC>,
> + <&gcc UFS_PHY_GDSC>;
> + power-domain-names = "ufs_card_gdsc", "ufs_phy_gdsc";
Strange, but I don't see neither UFS_PHY_GDSC nor UFS_CARD_GDSC in
gcc-sm8150.c [1] (and accordingly not in
include/dt-bindings/clock/qcom,gcc-sm8150.h), but they are present in
corresponding files for sm8250 [2].
By quick look at downstream sm8150-gdsc.dtsi addresses seem to be
similar to one used on sm8250, so I'm guessing gcc-sm8150 has to be
fixed first for this patch to work?
[1]
https://elixir.bootlin.com/linux/v5.17-rc1/source/drivers/clk/qcom/gcc-sm8150.c#L3716
[2]
https://elixir.bootlin.com/linux/v5.17-rc1/source/drivers/clk/qcom/gcc-sm8250.c#L3522
--
Regards
Alexey Minnekhanov
postmarketOS developer
https://www.postmarketos.org
^ permalink raw reply
* Re: [PATCH net-next 3/7] net: lan966x: Add support for ptp clocks
From: Horatiu Vultur @ 2022-01-28 13:48 UTC (permalink / raw)
To: Richard Cochran
Cc: netdev, devicetree, linux-kernel, davem, kuba, robh+dt,
UNGLinuxDriver, linux, f.fainelli, vivien.didelot,
vladimir.oltean, andrew
In-Reply-To: <20220127152841.GC20642@hoboy.vegasvil.org>
The 01/27/2022 07:28, Richard Cochran wrote:
>
> On Thu, Jan 27, 2022 at 11:23:29AM +0100, Horatiu Vultur wrote:
>
> > +static int lan966x_ptp_phc_init(struct lan966x *lan966x,
> > + int index,
> > + struct ptp_clock_info *clock_info)
> > +{
> > + struct lan966x_phc *phc = &lan966x->phc[index];
> > +
> > + phc->info = *clock_info;
> > + phc->clock = ptp_clock_register(&phc->info, lan966x->dev);
> > + if (IS_ERR(phc->clock))
> > + return PTR_ERR(phc->clock);
> > +
> > + phc->index = index;
> > + phc->lan966x = lan966x;
> > +
> > + /* PTP Rx stamping is always enabled. */
> > + phc->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
>
> Not true -- you allow it to be disabled in the next patch!
Actually the other patch is wrong. The HW will timestamp all the frames.
I will update the other patch in the next version.
>
> Thanks,
> Richard
>
>
> > +
> > + return 0;
> > +}
--
/Horatiu
^ permalink raw reply
* [PATCH] dt-bindings: net: can: fix dtbs warning
From: Dinh Nguyen @ 2022-01-28 13:31 UTC (permalink / raw)
To: robh+dt; +Cc: dinguyen, mkl, wg, linux-can, netdev, devicetree
Mute the warning from "make dtbs_check":
Documentation/devicetree/bindings/net/can/bosch,m_can.example.dt.yaml:
can@20e8000: bosch,mram-cfg: [[0, 0, 0, 32, 0, 0, 0, 1]] is too short
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
index 401ab7cdb379..035964a8609c 100644
--- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
+++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
@@ -101,6 +101,7 @@ properties:
- description: Tx Buffers 0-32 elements / 0-576 words
minimum: 0
maximum: 32
+ minItems: 1
power-domains:
description:
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v20 2/3] Input: mt6779-keypad - Add MediaTek keypad driver
From: Andy Shevchenko @ 2022-01-28 13:23 UTC (permalink / raw)
To: Mattijs Korpershoek
Cc: Dmitry Torokhov, Marco Felsch, Rob Herring, Matthias Brugger,
Fengping Yu, Yingjoe Chen, Fabien Parent, Kevin Hilman,
linux-input, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel
In-Reply-To: <87v8y4p483.fsf@baylibre.com>
On Fri, Jan 28, 2022 at 11:03:08AM +0100, Mattijs Korpershoek wrote:
> On Thu, Jan 27, 2022 at 17:20, Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> > On Thu, Jan 27, 2022 at 12:15:25PM +0100, Mattijs Korpershoek wrote:
...
> > Up to you.
> Thank you for your review and your suggestions.
Yes, as I said it you need a new version and consider them good.
Thanks!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH net-next 4/7] net: lan966x: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMP
From: Horatiu Vultur @ 2022-01-28 13:20 UTC (permalink / raw)
To: Richard Cochran
Cc: netdev, devicetree, linux-kernel, davem, kuba, robh+dt,
UNGLinuxDriver, linux, f.fainelli, vivien.didelot,
vladimir.oltean, andrew
In-Reply-To: <20220127215508.GA26514@hoboy.vegasvil.org>
The 01/27/2022 13:55, Richard Cochran wrote:
>
> On Thu, Jan 27, 2022 at 11:23:30AM +0100, Horatiu Vultur wrote:
>
> > diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c b/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
> > index 69d8f43e2b1b..9ff4d3fca5a1 100644
> > --- a/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
> > +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
> > @@ -35,6 +35,90 @@ static u64 lan966x_ptp_get_nominal_value(void)
> > return res;
> > }
> >
> > +int lan966x_ptp_hwtstamp_set(struct lan966x_port *port, struct ifreq *ifr)
> > +{
> > + struct lan966x *lan966x = port->lan966x;
> > + bool l2 = false, l4 = false;
> > + struct hwtstamp_config cfg;
> > + struct lan966x_phc *phc;
> > +
> > + /* For now don't allow to run ptp on ports that are part of a bridge,
> > + * because in case of transparent clock the HW will still forward the
> > + * frames, so there would be duplicate frames
> > + */
> > + if (lan966x->bridge_mask & BIT(port->chip_port))
> > + return -EINVAL;
> > +
> > + if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
> > + return -EFAULT;
> > +
> > + switch (cfg.tx_type) {
> > + case HWTSTAMP_TX_ON:
> > + port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
> > + break;
> > + case HWTSTAMP_TX_ONESTEP_SYNC:
> > + port->ptp_cmd = IFH_REW_OP_ONE_STEP_PTP;
> > + break;
> > + case HWTSTAMP_TX_OFF:
> > + port->ptp_cmd = IFH_REW_OP_NOOP;
> > + break;
> > + default:
> > + return -ERANGE;
> > + }
> > +
> > + mutex_lock(&lan966x->ptp_lock);
>
> No need to lock stack variables. Move locking down to ...
Good catch, will do that.
>
> > + switch (cfg.rx_filter) {
> > + case HWTSTAMP_FILTER_NONE:
> > + break;
> > + case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
> > + case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
> > + case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
> > + l4 = true;
> > + break;
> > + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
> > + case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
> > + case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
> > + l2 = true;
> > + break;
> > + case HWTSTAMP_FILTER_PTP_V2_EVENT:
> > + case HWTSTAMP_FILTER_PTP_V2_SYNC:
> > + case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
> > + l2 = true;
> > + l4 = true;
> > + break;
> > + default:
> > + mutex_unlock(&lan966x->ptp_lock);
> > + return -ERANGE;
> > + }
> > +
> > + if (l2 && l4)
> > + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
> > + else if (l2)
> > + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
> > + else if (l4)
> > + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
> > + else
> > + cfg.rx_filter = HWTSTAMP_FILTER_NONE;
> > +
> > + /* Commit back the result & save it */
>
> ... here
>
> > + phc = &lan966x->phc[LAN966X_PHC_PORT];
> > + memcpy(&phc->hwtstamp_config, &cfg, sizeof(cfg));
> > + mutex_unlock(&lan966x->ptp_lock);
> > +
> > + return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
> > +}
>
> Thanks,
> Richard
--
/Horatiu
^ permalink raw reply
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