* [PATCH 3/5] mfd: exynos-lpass: Drop unneeded syscon.h include
From: Krzysztof Kozlowski @ 2022-01-29 17:53 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
Greg Kroah-Hartman, Sylwester Nawrocki, Marek Szyprowski,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
linux-serial
In-Reply-To: <20220129175332.298666-1-krzysztof.kozlowski@canonical.com>
syscon regmap is not used since commit addebf1588ab ("mfd: exynos-lpass:
Remove pad retention control").
Fixes: addebf1588ab ("mfd: exynos-lpass: Remove pad retention control")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
drivers/mfd/exynos-lpass.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 99bd0e73c19c..166cd21088cd 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -15,7 +15,6 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
--
2.32.0
^ permalink raw reply related
* [PATCH 4/5] dt-bindings: mfd: samsung,exynos5433-lpass: Convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:53 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
Greg Kroah-Hartman, Sylwester Nawrocki, Marek Szyprowski,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
linux-serial
In-Reply-To: <20220129175332.298666-1-krzysztof.kozlowski@canonical.com>
Convert the Exynos5433 LPASS bindings to DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/mfd/samsung,exynos5433-lpass.txt | 72 -----------
.../mfd/samsung,exynos5433-lpass.yaml | 119 ++++++++++++++++++
2 files changed, 119 insertions(+), 72 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
create mode 100644 Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml
diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
deleted file mode 100644
index 30ea27c3936d..000000000000
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
-
-Required properties:
-
- - compatible : "samsung,exynos5433-lpass"
- - reg : should contain the LPASS top SFR region location
- and size
- - clock-names : should contain following required clocks: "sfr0_ctrl"
- - clocks : should contain clock specifiers of all clocks, which
- input names have been specified in clock-names
- property, in same order.
- - #address-cells : should be 1
- - #size-cells : should be 1
- - ranges : must be present
-
-Each IP block of the Low Power Audio Subsystem should be specified as
-an optional sub-node. For "samsung,exynos5433-lpass" compatible this includes:
-UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
-
-Bindings of the sub-nodes are described in:
- ../serial/samsung_uart.yaml
- ../sound/samsung-i2s.txt
- ../dma/arm-pl330.txt
-
-
-Example:
-
-audio-subsystem {
- compatible = "samsung,exynos5433-lpass";
- reg = <0x11400000 0x100>, <0x11500000 0x08>;
- clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
- clock-names = "sfr0_ctrl";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- adma: adma@11420000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x11420000 0x1000>;
- interrupts = <0 73 0>;
- clocks = <&cmu_aud CLK_ACLK_DMAC>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- i2s0: i2s0@11440000 {
- compatible = "samsung,exynos7-i2s";
- reg = <0x11440000 0x100>;
- dmas = <&adma 0 &adma 2>;
- dma-names = "tx", "rx";
- interrupts = <0 70 0>;
- clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
- <&cmu_aud CLK_SCLK_AUD_I2S>,
- <&cmu_aud CLK_SCLK_I2S_BCLK>;
- clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_bus>;
- };
-
- serial_3: serial@11460000 {
- compatible = "samsung,exynos5433-uart";
- reg = <0x11460000 0x100>;
- interrupts = <0 67 0>;
- clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
- <&cmu_aud CLK_SCLK_AUD_UART>;
- clock-names = "uart", "clk_uart_baud0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart_aud_bus>;
- };
- };
diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml
new file mode 100644
index 000000000000..96ef6113c8bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/samsung,exynos5433-lpass.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ const: samsung,exynos5433-lpass
+
+ '#address-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: sfr0_ctrl
+
+ power-domains:
+ maxItems: 1
+
+ ranges: true
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^dma-controller@[0-9a-f]+$":
+ $ref: /schemas/dma/arm,pl330.yaml
+
+ "^i2s@[0-9a-f]+$":
+ $ref: /schemas/sound/samsung-i2s.yaml
+
+ "^serial@[0-9a-f]+$":
+ $ref: /schemas/serial/samsung_uart.yaml
+
+required:
+ - compatible
+ - '#address-cells'
+ - clocks
+ - clock-names
+ - ranges
+ - reg
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ audio-subsystem@11400000 {
+ compatible = "samsung,exynos5433-lpass";
+ reg = <0x11400000 0x100>, <0x11500000 0x08>;
+ clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+ clock-names = "sfr0_ctrl";
+ power-domains = <&pd_aud>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma-controller@11420000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x11420000 0x1000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_aud CLK_ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ power-domains = <&pd_aud>;
+ };
+
+ i2s@11440000 {
+ compatible = "samsung,exynos7-i2s";
+ reg = <0x11440000 0x100>;
+ dmas = <&adma 0>, <&adma 2>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
+ <&cmu_aud CLK_SCLK_AUD_I2S>,
+ <&cmu_aud CLK_SCLK_I2S_BCLK>;
+ clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_bus>;
+ power-domains = <&pd_aud>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ serial@11460000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x11460000 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
+ <&cmu_aud CLK_SCLK_AUD_UART>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_aud_bus>;
+ power-domains = <&pd_aud>;
+ status = "disabled";
+ };
+ };
--
2.32.0
^ permalink raw reply related
* [PATCH 5/5] dt-bindings: serial: samsung_uart: Document Exynos5433 compatible
From: Krzysztof Kozlowski @ 2022-01-29 17:53 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
Greg Kroah-Hartman, Sylwester Nawrocki, Marek Szyprowski,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
linux-serial
In-Reply-To: <20220129175332.298666-1-krzysztof.kozlowski@canonical.com>
Document the Exynos5433 UART compatible, supported since commit
31ec77aca72e ("serial: samsung: Add the support for Exynos5433 SoC").
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index 2940afb874b3..6aceba4a5f79 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -26,6 +26,7 @@ properties:
- samsung,s3c6400-uart
- samsung,s5pv210-uart
- samsung,exynos4210-uart
+ - samsung,exynos5433-uart
- samsung,exynos850-uart
reg:
@@ -111,6 +112,7 @@ allOf:
enum:
- apple,s5l-uart
- samsung,exynos4210-uart
+ - samsung,exynos5433-uart
then:
properties:
clocks:
--
2.32.0
^ permalink raw reply related
* [PATCH] arm64: dts: rockchip: align pl330 node name with dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:54 UTC (permalink / raw)
To: Rob Herring, Heiko Stuebner, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
Cc: Krzysztof Kozlowski
Fixes dtbs_check warnings like:
dmac@ff240000: $nodename:0: 'dmac@ff240000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index f972704dfe7a..56dfbb2e2fa6 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -711,7 +711,7 @@ rktimer: timer@ff210000 {
clock-names = "pclk", "timer";
};
- dmac: dmac@ff240000 {
+ dmac: dma-controller@ff240000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff240000 0x0 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 39db0b85b4da..b822533dc7f1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -489,7 +489,7 @@ pwm3: pwm@ff1b0030 {
status = "disabled";
};
- dmac: dmac@ff1f0000 {
+ dmac: dma-controller@ff1f0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff1f0000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
--
2.32.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: lg: add dma-cells to pl330 node
From: Krzysztof Kozlowski @ 2022-01-29 17:55 UTC (permalink / raw)
To: Chanho Min, Rob Herring, linux-arm-kernel, devicetree,
linux-kernel
Cc: Krzysztof Kozlowski
dma-cells property is required for dma-controller. Fixes dtbs_check
warnings like:
dma@c1128000: '#dma-cells' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 1 +
arch/arm64/boot/dts/lg/lg1313.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 081fe7a9f605..ef57df716f14 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -188,6 +188,7 @@ dmac0: dma@c1128000 {
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
gpio0: gpio@fd400000 {
#gpio-cells = <2>;
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 604bb6975337..4e6b65939b72 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -188,6 +188,7 @@ dmac0: dma@c1128000 {
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
gpio0: gpio@fd400000 {
#gpio-cells = <2>;
--
2.32.0
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: lg: align pl330 node name with dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:55 UTC (permalink / raw)
To: Chanho Min, Rob Herring, linux-arm-kernel, devicetree,
linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20220129175514.298942-1-krzysztof.kozlowski@canonical.com>
Fixes dtbs_check warnings like:
dma@c1128000: $nodename:0: 'dma@c1128000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/lg/lg1312.dtsi | 2 +-
arch/arm64/boot/dts/lg/lg1313.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index ef57df716f14..bec97480a960 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -182,7 +182,7 @@ spi1: spi@fe900000 {
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
- dmac0: dma@c1128000 {
+ dmac0: dma-controller@c1128000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xc1128000 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 4e6b65939b72..ada3d4dc6305 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -182,7 +182,7 @@ spi1: spi@fe900000 {
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
- dmac0: dma@c1128000 {
+ dmac0: dma-controller@c1128000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xc1128000 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
--
2.32.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: stratix10: align pl330 node name with dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:55 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, devicetree, linux-kernel; +Cc: Krzysztof Kozlowski
Fixes dtbs_check warnings like:
pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 4124021768b1..da032a6f71da 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -333,7 +333,7 @@ ocram: sram@ffe00000 {
reg = <0xffe00000 0x100000>;
};
- pdma: pdma@ffda0000 {
+ pdma: dma-controller@ffda0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffda0000 0x1000>;
interrupts = <0 81 4>,
--
2.32.0
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: agilex: align pl330 node name with dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:55 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, devicetree, linux-kernel; +Cc: Krzysztof Kozlowski
In-Reply-To: <20220129175535.299035-1-krzysztof.kozlowski@canonical.com>
Fixes dtbs_check warnings like:
pdma@ffda0000: $nodename:0: 'pdma@ffda0000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 63dd4e69c962..1f4618c1062e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -337,7 +337,7 @@ ocram: sram@ffe00000 {
reg = <0xffe00000 0x40000>;
};
- pdma: pdma@ffda0000 {
+ pdma: dma-controller@ffda0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffda0000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
--
2.32.0
^ permalink raw reply related
* [PATCH] arm64: dts: broadcom: align pl330 node name with dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:55 UTC (permalink / raw)
To: Ray Jui, Scott Branden, bcm-kernel-feedback-list, Rob Herring,
linux-arm-kernel, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
Fixes dtbs_check warnings like:
dma@310000: $nodename:0: 'dma@310000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +-
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index 2cfeaf3b0a87..6da38ac317f2 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -276,7 +276,7 @@ crypto3: crypto@61330000 {
mboxes = <&pdc3 0>;
};
- dma0: dma@61360000 {
+ dma0: dma-controller@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 7b04dfe67bef..4135246b6e72 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -543,7 +543,7 @@ hwrng: hwrng@220000 {
reg = <0x00220000 0x28>;
};
- dma0: dma@310000 {
+ dma0: dma-controller@310000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x00310000 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
--
2.32.0
^ permalink raw reply related
* [PATCH] arm64: dts: juno: align pl330 node name with dtschema
From: Krzysztof Kozlowski @ 2022-01-29 17:56 UTC (permalink / raw)
To: Liviu Dudau, Sudeep Holla, Lorenzo Pieralisi, Rob Herring,
linux-arm-kernel, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
Fixes dtbs_check warning:
dma@7ff00000: $nodename:0: 'dma@7ff00000' does not match '^dma-controller(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 6288e104a089..af499049cb00 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -672,7 +672,7 @@ smmu_usb: iommu@7fb30000 {
dma-coherent;
};
- dma@7ff00000 {
+ dma-controller@7ff00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x7ff00000 0 0x1000>;
#dma-cells = <1>;
--
2.32.0
^ permalink raw reply related
* Re: [PATCH 1/2] arm64: dts: rockchip: fix vcc3v3_lcd{0,1}_n regulators in rk3568-evb1-10
From: Heiko Stuebner @ 2022-01-29 17:57 UTC (permalink / raw)
To: linux-rockchip, linux-kernel, Michael Riesch, linux-arm-kernel,
devicetree
Cc: Heiko Stuebner, Rob Herring, Liang Chen, sha
In-Reply-To: <20220129162440.5415-1-michael.riesch@wolfvision.net>
On Sat, 29 Jan 2022 17:24:39 +0100, Michael Riesch wrote:
> The voltages VCC3V3_LCD{0,1} can be enabled with the pins GPIO0_C7 and
> GPIO0_C5, respectively. This patch modifies the device tree in order to
> reflect this.
Applied, thanks!
[1/2] arm64: dts: rockchip: fix vcc3v3_lcd{0,1}_n regulators in rk3568-evb1-10
commit: 9ade1ab4d85f5fc31a5d6cf5147702ed5c1b5b10
[2/2] arm64: dts: rockchip: add the touchscreen controller to rk3568-evb1-v10
commit: 922237a6c211d9fe46b5dfb56307872cdced386d
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v2 0/4] Quartz64-A fixes and enablement from 5.17-rc1
From: Heiko Stuebner @ 2022-01-29 17:57 UTC (permalink / raw)
To: Peter Geis
Cc: Heiko Stuebner, Rob Herring, linux-kernel, linux-rockchip,
linux-arm-kernel, devicetree
In-Reply-To: <20220128003809.3291407-1-pgwipeout@gmail.com>
On Thu, 27 Jan 2022 19:38:04 -0500, Peter Geis wrote:
> Good Evening,
>
> This is the first of several patch series for further expanding
> Quartz64-A support.
>
> This series has the following patches:
> Fix the ddr regulator voltage.
> Add pmu_io_domains to permit sdio and high speed emmc support.
> Add sdmmc1 node for wifi support.
> Annotate con40 functions and enable i2c3.
>
> [...]
Applied, thanks!
[1/4] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage
commit: 8c318aaa20000bcfb9dc115c2a8e08c2e77ad439
[2/4] arm64: dts: rockchip: add Quartz64-A pmu_io_domains
commit: 827dfba89ae150cd0fd88bc13117540cb4882943
[3/4] arm64: dts: rockchip: add Quartz64-A sdmmc1 node
commit: 2ed1e35457a1917a9c567c186a5adc7ce6341b6e
With a minimal reordering (sdio-* comes before spdif alphabetically)
[4/4] arm64: dts: rockchip: add Quartz64-A con40 hardware
commit: 2943660fe301aa650cdf60226a2a350d09145823
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity
From: Heiko Stuebner @ 2022-01-29 17:57 UTC (permalink / raw)
To: quentin.schulz@theobroma-systems.com, robh+dt
Cc: Heiko Stuebner, Jakob Unterwurzacher, linux-kernel,
linux-rockchip, Quentin Schulz, linux-arm-kernel, devicetree
In-Reply-To: <20220119134948.1444965-1-quentin.schulz@theobroma-systems.com>
On Wed, 19 Jan 2022 14:49:48 +0100, quentin.schulz@theobroma-systems.com wrote:
> There are signal integrity issues running the eMMC at 200MHz on Puma
> RK3399-Q7.
>
> Similar to the work-around found for RK3399 Gru boards, lowering the
> frequency to 100MHz made the eMMC much more stable, so let's lower the
> frequency to 100MHz.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: fix rk3399-puma eMMC HS400 signal integrity
commit: 7623e16af6bac131305292eb99cea988adbf0484
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH net-next v4 0/3] Cadence MACB/GEM support for ZynqMP SGMII
From: patchwork-bot+netdevbpf @ 2022-01-29 18:00 UTC (permalink / raw)
To: Robert Hancock
Cc: netdev, davem, kuba, robh+dt, michal.simek, nicolas.ferre,
claudiu.beznea, devicetree, linux, laurent.pinchart
In-Reply-To: <20220127163736.3677478-1-robert.hancock@calian.com>
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Thu, 27 Jan 2022 10:37:33 -0600 you wrote:
> Changes to allow SGMII mode to work properly in the GEM driver on the
> Xilinx ZynqMP platform.
>
> Changes since v3:
> -more code formatting and error handling fixes
>
> Changes since v2:
> -fixed missing includes in DT binding example
> -fixed phy_init and phy_power_on error handling/cleanup, moved
> phy_power_on to open rather than probe
>
> [...]
Here is the summary with links:
- [net-next,v4,1/3] dt-bindings: net: cdns,macb: added generic PHY and reset mappings for ZynqMP
https://git.kernel.org/netdev/net-next/c/f4ea385a16c5
- [net-next,v4,2/3] net: macb: Added ZynqMP-specific initialization
https://git.kernel.org/netdev/net-next/c/8b73fa3ae02b
- [net-next,v4,3/3] arm64: dts: zynqmp: Added GEM reset definitions
https://git.kernel.org/netdev/net-next/c/e461bd6f43f4
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: align pl330 node name with dtschema
From: Heiko Stuebner @ 2022-01-29 18:01 UTC (permalink / raw)
To: Rob Herring, linux-kernel, linux-rockchip, Krzysztof Kozlowski,
devicetree, linux-arm-kernel
Cc: Heiko Stuebner
In-Reply-To: <20220129175429.298836-1-krzysztof.kozlowski@canonical.com>
On Sat, 29 Jan 2022 18:54:29 +0100, Krzysztof Kozlowski wrote:
> Fixes dtbs_check warnings like:
>
> dmac@ff240000: $nodename:0: 'dmac@ff240000' does not match '^dma-controller(@.*)?$'
Applied, thanks!
[1/1] arm64: dts: rockchip: align pl330 node name with dtschema
commit: 3d7eaaa2fda44a5d11efdb1069664dba6ee49ee0
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic dt parse in opensbi
From: Marc Zyngier @ 2022-01-29 18:32 UTC (permalink / raw)
To: guoren
Cc: anup, tglx, palmer, samuel, linux-kernel, linux-riscv, devicetree,
Guo Ren
In-Reply-To: <20220129162726.1154501-3-guoren@kernel.org>
On Sat, 29 Jan 2022 16:27:26 +0000,
guoren@kernel.org wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> The thead,c900-plic has been used in opensbi to distinguish
> PLIC [1]. Although PLICs have the same behaviors in Linux,
> they are different hardware with some custom initializing in
> firmware(opensbi).
>
> [1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Cc: Anup Patel <anup@brainfault.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Samuel Holland <samuel@sholland.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
> drivers/irqchip/irq-sifive-plic.c | 25 +++++++++++++++++++++++--
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index 259065d271ef..245655928076 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -172,7 +172,7 @@ static void plic_irq_eoi(struct irq_data *d)
> }
> }
>
> -static struct irq_chip plic_chip = {
> +static struct irq_chip sifive_plic_chip = {
> .name = "SiFive PLIC",
> .irq_mask = plic_irq_mask,
> .irq_unmask = plic_irq_unmask,
> @@ -182,12 +182,24 @@ static struct irq_chip plic_chip = {
> #endif
> };
>
> +static struct irq_chip thead_plic_chip = {
> + .name = "T-Head PLIC",
> + .irq_mask = plic_irq_mask,
> + .irq_unmask = plic_irq_unmask,
> + .irq_eoi = plic_irq_eoi,
> +#ifdef CONFIG_SMP
> + .irq_set_affinity = plic_set_affinity,
> +#endif
> +};
For pure entertainment, let's compare the two structures:
static struct irq_chip plic_chip = {
.name = "SiFive PLIC",
.irq_mask = plic_irq_mask,
.irq_unmask = plic_irq_unmask,
.irq_eoi = plic_irq_eoi,
#ifdef CONFIG_SMP
.irq_set_affinity = plic_set_affinity,
#endif
};
Oh wait: a string. Must be really important. Not.
> +
> +static struct irq_chip *def_plic_chip = &sifive_plic_chip;
> +
> static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
> irq_hw_number_t hwirq)
> {
> struct plic_priv *priv = d->host_data;
>
> - irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
> + irq_domain_set_info(d, irq, hwirq, def_plic_chip, d->host_data,
> handle_fasteoi_irq, NULL, NULL);
> irq_set_noprobe(irq);
> irq_set_affinity(irq, &priv->lmask);
> @@ -396,5 +408,14 @@ static int __init plic_init(struct device_node *node,
> return error;
> }
>
> +static int __init thead_c900_plic_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + def_plic_chip = &thead_plic_chip;
> +
> + return plic_init(node, parent);
> +}
> +
> IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
> +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
Sorry, but I can't see any point to this patch.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH] dt-bindings: net: dsa: realtek-smi: convert to YAML schema
From: Arınç ÜNAL @ 2022-01-29 19:35 UTC (permalink / raw)
To: Luiz Angelo Daros de Luca, Rob Herring, Alvin Šipraga,
Linus Walleij
Cc: devicetree, Arnd Bergmann, Olof Johansson, Florian Fainelli,
Stephen Rothwell, Andrew Lunn, Vivien Didelot, Vladimir Oltean,
David S . Miller, Jakub Kicinski, open list:NETWORKING DRIVERS,
open list
In-Reply-To: <CAJq09z4G40ttsTHXtOywjyusNLSjt_BQ9D78PhwSodJr=4p6OA@mail.gmail.com>
On 29/01/2022 19:02, Luiz Angelo Daros de Luca wrote:
> Thanks Rob, now that the code side is merged, I'm back to docs.
>
>
>>> + interrupt-controller:
>>> + description: see interrupt-controller/interrupts.txt
>>
>> Don't need generic descriptions. Just 'true' here is fine.
>
> Do you really mean quoted true, like in "description: 'true' "?
> Without quotes it will fail
>>
>>> +
>>> + interrupts:
>>> + description: TODO
>>
>> You have to define how many interrupts and what they are.
>
> I didn't write the interruption code and Linus and Alvin might help here.
>
> The switch has a single interrupt pin that signals an interruption happened.
> The code reads a register to multiplex to these interruptions:
>
> INT_TYPE_LINK_STATUS = 0,
> INT_TYPE_METER_EXCEED,
> INT_TYPE_LEARN_LIMIT,
> INT_TYPE_LINK_SPEED,
> INT_TYPE_CONGEST,
> INT_TYPE_GREEN_FEATURE,
> INT_TYPE_LOOP_DETECT,
> INT_TYPE_8051,
> INT_TYPE_CABLE_DIAG,
> INT_TYPE_ACL,
> INT_TYPE_RESERVED, /* Unused */
> INT_TYPE_SLIENT,
>
> And most of them, but not all, multiplex again to each port.
>
> However, the linux driver today does not care about any of these
> interruptions but INT_TYPE_LINK_STATUS. So it simply multiplex only
> this the interruption to each port, in a n-cell map (n being number of
> ports).
> I don't know what to describe here as device-tree should be something
> independent of a particular OS or driver.
>
> Anyway, I doubt someone might want to plug one of these interruptions
> outside the switch driver. Could it be simple as this:
>
> interrupts:
> minItems: 3
> maxItems: 10
> description:
> interrupt mapping one per switch port
>
> Once realtek-smi.yaml settles, I'll also send the realtek-mdio.yaml.
Why not turn realtek-smi.yaml into realtek.yaml which would also contain
information for the mdio interface? The things different with using MDIO
are that we don't use the [mdc,mdio,reset]-gpios properties and don't
handle the PHYs to the DSA ports. Couldn't you present these differences
on a single YAML file?
Arınç
^ permalink raw reply
* [PATCH 4/8] dt-bindings: phy: samsung,dp-video-phy: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung SoC DisplayPort PHY bindings to DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/phy/samsung,dp-video-phy.yaml | 41 +++++++++++++++++++
.../devicetree/bindings/phy/samsung-phy.txt | 11 -----
2 files changed, 41 insertions(+), 11 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml
new file mode 100644
index 000000000000..838c6d480ce6
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC DisplayPort PHY
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos5250-dp-video-phy
+ - samsung,exynos5420-dp-video-phy
+
+ "#phy-cells":
+ const: 0
+
+ samsung,pmu-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU system controller interface.
+
+required:
+ - compatible
+ - "#phy-cells"
+ - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ phy {
+ compatible = "samsung,exynos5420-dp-video-phy";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 6ab16734eb65..839ffe2a2d05 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -1,14 +1,3 @@
-Samsung Exynos SoC series Display Port PHY
--------------------------------------------------
-
-Required properties:
-- compatible : should be one of the following supported values:
- - "samsung,exynos5250-dp-video-phy"
- - "samsung,exynos5420-dp-video-phy"
-- samsung,pmu-syscon: phandle for PMU system controller interface, used to
- control pmu registers for power isolation.
-- #phy-cells : from the generic PHY bindings, must be 0;
-
Samsung S5P/Exynos SoC series USB PHY
-------------------------------------------------
--
2.32.0
^ permalink raw reply related
* [PATCH 2/8] dt-bindings: phy: samsung: drop old Eynos5440 PCIe phy
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
The Exynos5440 PCIe phy support was removed in commit 496db029142f
("phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433
PCIe PHY") (with its own bindings), so drop the old bindings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/phy/samsung-phy.txt | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 8f51aee91101..390065f49b62 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -191,20 +191,3 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
-
-Samsung Exynos SoC series PCIe PHY controller
---------------------------------------------------
-Required properties:
-- compatible : Should be set to "samsung,exynos5440-pcie-phy"
-- #phy-cells : Must be zero
-- reg : a register used by phy driver.
- - First is for phy register, second is for block register.
-- reg-names : Must be set to "phy" and "block".
-
-Example:
- pcie_phy0: pcie-phy@270000 {
- #phy-cells = <0>;
- compatible = "samsung,exynos5440-pcie-phy";
- reg = <0x270000 0x1000>, <0x271000 0x40>;
- reg-names = "phy", "block";
- };
--
2.32.0
^ permalink raw reply related
* [PATCH 1/8] arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
Use the same order of USB 3.0 DRD controller clocks as in Exynos5433.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 3364b09c3158..e38bb02a2152 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -684,11 +684,10 @@ usbdrd_phy: phy@15500000 {
reg = <0x15500000 0x100>;
clocks = <&clock_fsys0 ACLK_USBDRD300>,
<&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
- <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
<&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
+ <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
<&clock_fsys0 SCLK_USBDRD300_REFCLK>;
- clock-names = "phy", "ref", "phy_pipe",
- "phy_utmi", "itp";
+ clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
--
2.32.0
^ permalink raw reply related
* [PATCH 5/8] dt-bindings: phy: samsung,usb2-phy: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung SoC USB 2.0 PHY bindings to DT schema format.
Except the conversion, add also vbus-supply property which was already
used by the driver and DTS.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/phy/samsung,usb2-phy.yaml | 102 ++++++++++++++++++
.../devicetree/bindings/phy/samsung-phy.txt | 60 -----------
MAINTAINERS | 2 +-
3 files changed, 103 insertions(+), 61 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml
new file mode 100644
index 000000000000..056e270a4e88
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5P/Exynos SoC USB 2.0 PHY
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+description: |
+ The first phandle argument in the PHY specifier identifies the PHY, its
+ meaning is compatible dependent. For the currently supported SoCs (Exynos4210
+ and Exynos4212) it is as follows::
+ 0 - USB device ("device"),
+ 1 - USB host ("host"),
+ 2 - HSIC0 ("hsic0"),
+ 3 - HSIC1 ("hsic1"),
+ Exynos3250 has only USB device phy available as phy 0.
+
+ Exynos4210 and Exynos4212 use mode switching and require that mode switch
+ register is supplied.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos3250-usb2-phy
+ - samsung,exynos4210-usb2-phy
+ - samsung,exynos4x12-usb2-phy
+ - samsung,exynos5250-usb2-phy
+ - samsung,exynos5420-usb2-phy
+ - samsung,s5pv210-usb2-phy
+
+ clocks:
+ items:
+ - description: PHY module gate clock.
+ - description: Reference rate clock of PHY module.
+
+ clock-names:
+ items:
+ - const: phy
+ - const: ref
+
+ "#phy-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ samsung,pmureg-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU system controller interface.
+
+ samsung,sysreg-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to system registers interface.
+
+ vbus-supply:
+ description:
+ VBUS power source.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - "#phy-cells"
+ - reg
+ - samsung,pmureg-phandle
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos4x12-usb2-phy
+ - samsung,exynos5250-usb2-phy
+ - samsung,exynos5420-usb2-phy
+ then:
+ required:
+ - samsung,sysreg-phandle
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5420.h>
+
+ phy@12130000 {
+ compatible = "samsung,exynos5420-usb2-phy";
+ reg = <0x12130000 0x100>;
+ #phy-cells = <1>;
+ clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,sysreg-phandle = <&sysreg_system_controller>;
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 839ffe2a2d05..d26ac7401258 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -1,63 +1,3 @@
-Samsung S5P/Exynos SoC series USB PHY
--------------------------------------------------
-
-Required properties:
-- compatible : should be one of the listed compatibles:
- - "samsung,exynos3250-usb2-phy"
- - "samsung,exynos4210-usb2-phy"
- - "samsung,exynos4x12-usb2-phy"
- - "samsung,exynos5250-usb2-phy"
- - "samsung,exynos5420-usb2-phy"
- - "samsung,s5pv210-usb2-phy"
-- reg : a list of registers used by phy driver
- - first and obligatory is the location of phy modules registers
-- samsung,sysreg-phandle - handle to syscon used to control the system registers
-- samsung,pmureg-phandle - handle to syscon used to control PMU registers
-- #phy-cells : from the generic phy bindings, must be 1;
-- clocks and clock-names:
- - the "phy" clock is required by the phy module, used as a gate
- - the "ref" clock is used to get the rate of the clock provided to the
- PHY module
-
-Optional properties:
-- vbus-supply: power-supply phandle for vbus power source
-
-The first phandle argument in the PHY specifier identifies the PHY, its
-meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
-and Exynos 4212) it is as follows:
- 0 - USB device ("device"),
- 1 - USB host ("host"),
- 2 - HSIC0 ("hsic0"),
- 3 - HSIC1 ("hsic1"),
-Exynos3250 has only USB device phy available as phy 0.
-
-Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
-register is supplied.
-
-Example:
-
-For Exynos 4412 (compatible with Exynos 4212):
-
-usbphy: phy@125b0000 {
- compatible = "samsung,exynos4x12-usb2-phy";
- reg = <0x125b0000 0x100>;
- clocks = <&clock 305>, <&clock 2>;
- clock-names = "phy", "ref";
- #phy-cells = <1>;
- samsung,sysreg-phandle = <&sys_reg>;
- samsung,pmureg-phandle = <&pmu_reg>;
-};
-
-Then the PHY can be used in other nodes such as:
-
-phy-consumer@12340000 {
- phys = <&usbphy 2>;
- phy-names = "phy";
-};
-
-Refer to DT bindings documentation of particular PHY consumer devices for more
-information about required PHYs and the way of specification.
-
Samsung SATA PHY Controller
---------------------------
diff --git a/MAINTAINERS b/MAINTAINERS
index ddcee331dc09..46f6ced8370a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17168,7 +17168,7 @@ SAMSUNG USB2 PHY DRIVER
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
L: linux-kernel@vger.kernel.org
S: Supported
-F: Documentation/devicetree/bindings/phy/samsung-phy.txt
+F: Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml
F: Documentation/driver-api/phy/samsung-usb2.rst
F: drivers/phy/samsung/phy-exynos4210-usb2.c
F: drivers/phy/samsung/phy-exynos4x12-usb2.c
--
2.32.0
^ permalink raw reply related
* [PATCH 6/8] dt-bindings: phy: samsung,exynos5250-sata-phy: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung Exynos5250 SoC SATA PHY bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../phy/samsung,exynos5250-sata-phy.yaml | 64 +++++++++++++++++++
.../devicetree/bindings/phy/samsung-phy.txt | 26 --------
2 files changed, 64 insertions(+), 26 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos5250-sata-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos5250-sata-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos5250-sata-phy.yaml
new file mode 100644
index 000000000000..62b39bb46585
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos5250-sata-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5250 SoC SATA PHY
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+properties:
+ compatible:
+ const: samsung,exynos5250-sata-phy
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: sata_phyctrl
+
+ "#phy-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ samsung,syscon-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU system controller interface.
+
+ samsung,exynos-sataphy-i2c-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to I2C SATA interface.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - "#phy-cells"
+ - reg
+ - samsung,syscon-phandle
+ - samsung,exynos-sataphy-i2c-phandle
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5250.h>
+
+ phy@12170000 {
+ compatible = "samsung,exynos5250-sata-phy";
+ reg = <0x12170000 0x1ff>;
+ clocks = <&clock CLK_SATA_PHYCTRL>;
+ clock-names = "sata_phyctrl";
+ #phy-cells = <0>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index d26ac7401258..1ee78016dc72 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -1,29 +1,3 @@
-Samsung SATA PHY Controller
----------------------------
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
-- reg : offset and length of the SATA PHY register set;
-- #phy-cells : must be zero
-- clocks : must be exactly one entry
-- clock-names : must be "sata_phyctrl"
-- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
-- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
-
-Example:
- sata_phy: sata-phy@12170000 {
- compatible = "samsung,exynos5250-sata-phy";
- reg = <0x12170000 0x1ff>;
- clocks = <&clock 287>;
- clock-names = "sata_phyctrl";
- #phy-cells = <0>;
- samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
- samsung,syscon-phandle = <&pmu_syscon>;
- };
-
Device-Tree bindings for sataphy i2c client driver
--------------------------------------------------
--
2.32.0
^ permalink raw reply related
* [PATCH 7/8] dt-bindings: phy: samsung: move SATA phy I2C to trivial devices
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
The I2C interface for Samsung Exynos SoC SATA phy is a very simple and
limited, so move it to trivial devices.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/phy/samsung-phy.txt | 14 --------------
.../devicetree/bindings/trivial-devices.yaml | 2 ++
2 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 1ee78016dc72..b0abeb4ac0a2 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -1,17 +1,3 @@
-Device-Tree bindings for sataphy i2c client driver
---------------------------------------------------
-
-Required properties:
-compatible: Should be "samsung,exynos-sataphy-i2c"
-- reg: I2C address of the sataphy i2c device.
-
-Example:
-
- sata_phy_i2c:sata-phy@38 {
- compatible = "samsung,exynos-sataphy-i2c";
- reg = <0x38>;
- };
-
Samsung Exynos5 SoC series USB DRD PHY controller
--------------------------------------------------
diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml
index 091792ba993e..d53a4b2f81aa 100644
--- a/Documentation/devicetree/bindings/trivial-devices.yaml
+++ b/Documentation/devicetree/bindings/trivial-devices.yaml
@@ -283,6 +283,8 @@ properties:
- renesas,isl29501
# S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
- samsung,24ad0xd1
+ # Samsung Exynos SoC SATA PHY I2C device
+ - samsung,exynos-sataphy-i2c
# Sensirion low power multi-pixel gas sensor with I2C interface
- sensirion,sgpc3
# Sensirion multi-pixel gas sensor with I2C interface
--
2.32.0
^ permalink raw reply related
* [PATCH 8/8] dt-bindings: phy: samsung,usb3-drd-phy: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung Exynos USB 3.0 DRD PHY bindings to DT schema format.
Except the conversion, add also vbus-supply and vbus-boost-supply
properties which were already used by the driver and DTS.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/phy/samsung,usb3-drd-phy.yaml | 126 ++++++++++++++++++
.../devicetree/bindings/phy/samsung-phy.txt | 53 --------
2 files changed, 126 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/samsung-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
new file mode 100644
index 000000000000..f83f0f8135b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+description: |
+ For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
+ compatible PHYs, the second cell in the PHY specifier identifies the
+ PHY id, which is interpreted as follows::
+ 0 - UTMI+ type phy,
+ 1 - PIPE3 type phy.
+
+ For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
+ 'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
+ form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos5250-usbdrd-phy
+ - samsung,exynos5420-usbdrd-phy
+ - samsung,exynos5433-usbdrd-phy
+ - samsung,exynos7-usbdrd-phy
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+ description: |
+ At least two clocks::
+ - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
+ for register access.
+ - PHY reference clock (usually crystal clock), used for PHY operations,
+ associated by phy name. It is used to determine bit values for clock
+ settings register. For Exynos5420 this is given as 'sclk_usbphy30'
+ in the CMU.
+
+ "#phy-cells":
+ const: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Any connector to the data bus of this controller should be modelled using
+ the OF graph bindings specified.
+
+ reg:
+ maxItems: 1
+
+ samsung,pmu-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU system controller interface.
+
+ vbus-supply:
+ description:
+ VBUS power source.
+
+ vbus-boost-supply:
+ description:
+ VBUS Boost 5V power source.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - "#phy-cells"
+ - reg
+ - samsung,pmu-syscon
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5433-usbdrd-phy
+ - samsung,exynos7-usbdrd-phy
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+ clock-names:
+ items:
+ - const: phy
+ - const: ref
+ - const: phy_utmi
+ - const: phy_pipe
+ - const: itp
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: phy
+ - const: ref
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5420.h>
+
+ phy@12100000 {
+ compatible = "samsung,exynos5420-usbdrd-phy";
+ reg = <0x12100000 0x100>;
+ #phy-cells = <1>;
+ clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ vbus-supply = <&usb300_vbus_reg>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
deleted file mode 100644
index b0abeb4ac0a2..000000000000
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-Samsung Exynos5 SoC series USB DRD PHY controller
---------------------------------------------------
-
-Required properties:
-- compatible : Should be set to one of the following supported values:
- - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
- - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
- - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
- - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
-- reg : Register offset and length of USB DRD PHY register set;
-- clocks: Clock IDs array as required by the controller
-- clock-names: names of clocks correseponding to IDs in the clock property;
- Required clocks:
- - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
- used for register access.
- - ref: PHY's reference clock (usually crystal clock), used for
- PHY operations, associated by phy name. It is used to
- determine bit values for clock settings register.
- For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
- - optional clocks: Exynos5433 & Exynos7 SoC has now following additional
- gate clocks available:
- - phy_pipe: for PIPE3 phy
- - phy_utmi: for UTMI+ phy
- - itp: for ITP generation
-- samsung,pmu-syscon: phandle for PMU system controller interface, used to
- control pmu registers for power isolation.
-- #phy-cells : from the generic PHY bindings, must be 1;
-
-For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
-compatible PHYs, the second cell in the PHY specifier identifies the
-PHY id, which is interpreted as follows:
- 0 - UTMI+ type phy,
- 1 - PIPE3 type phy,
-
-Example:
- usbdrd_phy: usbphy@12100000 {
- compatible = "samsung,exynos5250-usbdrd-phy";
- reg = <0x12100000 0x100>;
- clocks = <&clock 286>, <&clock 1>;
- clock-names = "phy", "ref";
- samsung,pmu-syscon = <&pmu_system_controller>;
- #phy-cells = <1>;
- };
-
-- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
- 'usbdrd_phy' nodes should have numbered alias in the aliases node,
- in the form of usbdrdphyN, N = 0, 1... (depending on number of
- controllers).
-Example:
- aliases {
- usbdrdphy0 = &usb3_phy0;
- usbdrdphy1 = &usb3_phy1;
- };
--
2.32.0
^ permalink raw reply related
* [PATCH 3/8] dt-bindings: phy: samsung,mipi-video-phy: convert to dtschema
From: Krzysztof Kozlowski @ 2022-01-29 19:36 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring,
Krzysztof Kozlowski, Alim Akhtar, Sylwester Nawrocki,
Guenter Roeck, Marek Szyprowski, linux-phy, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc
In-Reply-To: <20220129193646.372481-1-krzysztof.kozlowski@canonical.com>
Convert the Samsung SoC MIPI CSIS/DSIM DPHY bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/phy/samsung,mipi-video-phy.yaml | 113 ++++++++++++++++++
.../devicetree/bindings/phy/samsung-phy.txt | 29 -----
2 files changed, 113 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
new file mode 100644
index 000000000000..54aa056b224d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+
+description: |
+ For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
+ PHY specifier identifies the PHY and its meaning is as follows::
+ 0 - MIPI CSIS 0,
+ 1 - MIPI DSIM 0,
+ 2 - MIPI CSIS 1,
+ 3 - MIPI DSIM 1.
+
+ samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy
+ support additional fifth PHY::
+ 4 - MIPI CSIS 2.
+
+properties:
+ compatible:
+ enum:
+ - samsung,s5pv210-mipi-video-phy
+ - samsung,exynos5420-mipi-video-phy
+ - samsung,exynos5433-mipi-video-phy
+
+ "#phy-cells":
+ const: 1
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU system controller interface, valid only for
+ samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy.
+
+ samsung,pmu-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU system controller interface, valid for
+ samsung,exynos5433-mipi-video-phy.
+
+ samsung,disp-sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to DISP system controller interface, valid for
+ samsung,exynos5433-mipi-video-phy.
+
+ samsung,cam0-sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to CAM0 system controller interface, valid for
+ samsung,exynos5433-mipi-video-phy.
+
+ samsung,cam1-sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to CAM1 system controller interface, valid for
+ samsung,exynos5433-mipi-video-phy.
+
+required:
+ - compatible
+ - "#phy-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,s5pv210-mipi-video-phy
+ - samsung,exynos5420-mipi-video-phy
+ then:
+ properties:
+ samsung,pmu-syscon: false
+ samsung,disp-sysreg: false
+ samsung,cam0-sysreg: false
+ samsung,cam1-sysreg: false
+ required:
+ - syscon
+ else:
+ properties:
+ syscon: false
+ required:
+ - samsung,pmu-syscon
+ - samsung,disp-sysreg
+ - samsung,cam0-sysreg
+ - samsung,cam1-sysreg
+
+additionalProperties: false
+
+examples:
+ - |
+ phy {
+ compatible = "samsung,exynos5433-mipi-video-phy";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,cam0-sysreg = <&syscon_cam0>;
+ samsung,cam1-sysreg = <&syscon_cam1>;
+ samsung,disp-sysreg = <&syscon_disp>;
+ };
+
+ - |
+ phy {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 390065f49b62..6ab16734eb65 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -1,32 +1,3 @@
-Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
--------------------------------------------------
-
-Required properties:
-- compatible : should be one of the listed compatibles:
- - "samsung,s5pv210-mipi-video-phy"
- - "samsung,exynos5420-mipi-video-phy"
- - "samsung,exynos5433-mipi-video-phy"
-- #phy-cells : from the generic phy bindings, must be 1;
-
-In case of s5pv210 and exynos5420 compatible PHYs:
-- syscon - phandle to the PMU system controller
-
-In case of exynos5433 compatible PHY:
- - samsung,pmu-syscon - phandle to the PMU system controller
- - samsung,disp-sysreg - phandle to the DISP system registers controller
- - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
- - samsung,cam1-sysreg - phandle to the CAM1 system registers controller
-
-For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
-the PHY specifier identifies the PHY and its meaning is as follows:
- 0 - MIPI CSIS 0,
- 1 - MIPI DSIM 0,
- 2 - MIPI CSIS 1,
- 3 - MIPI DSIM 1.
-"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
-supports additional fifth PHY:
- 4 - MIPI CSIS 2.
-
Samsung Exynos SoC series Display Port PHY
-------------------------------------------------
--
2.32.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox