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From: Mikko Perttunen <mperttunen@nvidia.com>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Thierry Reding <thierry.reding@kernel.org>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	webgeek1234@gmail.com
Cc: Thierry Reding <thierry.reding@gmail.com>,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, Aaron Kling <webgeek1234@gmail.com>,
	Azkali Manad <a.ffcc7@gmail.com>,
	Thomas Makin <halorocker89@gmail.com>
Subject: Re: [PATCH v2 2/2] soc/tegra: pmc: Add Tegra210B01 support
Date: Tue, 21 Jul 2026 16:22:30 +0900	[thread overview]
Message-ID: <rrmQkm06RD2JduKX6eSoDg@nvidia.com> (raw)
In-Reply-To: <20260720-t210b01-pmc-v2-2-ca5317f8507b@gmail.com>

On Monday, July 20, 2026 3:31 PM Aaron Kling via B4 Relay wrote:
> From: Azkali Manad <a.ffcc7@gmail.com>
> 
> The PMC in Tegra210B01 is very similar to the one in the original
> Tegra210, but has a few powergate differences. Add support for this soc.

The tables are a bit difficult to compare directly, so maybe list the 
differences between 210 and 210B01 in the commit message.

> 
> Signed-off-by: Azkali Manad <a.ffcc7@gmail.com>
> Co-developed-by: Thomas Makin <halorocker89@gmail.com>
> Signed-off-by: Thomas Makin <halorocker89@gmail.com>
> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
>  drivers/soc/tegra/pmc.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index f419a5395545f..48ae4ff3f00db 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -3897,6 +3897,67 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
>  	.has_single_mmio_aperture = true,
>  };
>  
> +static const char * const tegra210b01_powergates[] = {
> +	[TEGRA_POWERGATE_CPU] = "crail",
> +	[TEGRA_POWERGATE_3D] = "3d",
> +	[TEGRA_POWERGATE_PCIE] = "pcie",
> +	[TEGRA_POWERGATE_MPE] = "mpe",
> +	[TEGRA_POWERGATE_SATA] = "sata",

T210B01 doesn't have SATA, so this can be removed.

> +	[TEGRA_POWERGATE_CPU1] = "cpu1",
> +	[TEGRA_POWERGATE_CPU2] = "cpu2",
> +	[TEGRA_POWERGATE_CPU3] = "cpu3",
> +	[TEGRA_POWERGATE_CPU0] = "cpu0",
> +	[TEGRA_POWERGATE_C0NC] = "c0nc",
> +	[TEGRA_POWERGATE_SOR] = "sor",
> +	[TEGRA_POWERGATE_DIS] = "dis",
> +	[TEGRA_POWERGATE_DISB] = "disb",
> +	[TEGRA_POWERGATE_XUSBA] = "xusba",
> +	[TEGRA_POWERGATE_XUSBB] = "xusbb",
> +	[TEGRA_POWERGATE_XUSBC] = "xusbc",
> +	[TEGRA_POWERGATE_VIC] = "vic",
> +	[TEGRA_POWERGATE_IRAM] = "iram",
> +	[TEGRA_POWERGATE_NVDEC] = "nvdec",
> +	[TEGRA_POWERGATE_NVJPG] = "nvjpg",
> +	[TEGRA_POWERGATE_AUD] = "aud",
> +	[TEGRA_POWERGATE_DFD] = "dfd",
> +};
> +
> +static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
> +	.supports_core_domain = false,
> +	.num_powergates = ARRAY_SIZE(tegra210b01_powergates),
> +	.powergates = tegra210b01_powergates,
> +	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
> +	.cpu_powergates = tegra210_cpu_powergates,
> +	.has_tsense_reset = true,
> +	.has_gpu_clamps = true,
> +	.needs_mbist_war = false,
> +	.has_io_pad_wren = false,

Any particular reason to flip this to false? AFAICT it is still needed 
to make PWR_DET_VAL writable as on T210.

(The reset value is already (mostly) fine but seems prudent to write it 
anyway)

Thank you!
Mikko

> +	.maybe_tz_only = true,
> +	.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
> +	.io_pads = tegra210_io_pads,
> +	.num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls),
> +	.io_pad_vctrls = tegra210_io_pad_vctrls,
> +	.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
> +	.pin_descs = tegra210_pin_descs,
> +	.regs = &tegra20_pmc_regs,
> +	.init = tegra20_pmc_init,
> +	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
> +	.powergate_set = tegra114_powergate_set,
> +	.irq_set_wake = tegra210_pmc_irq_set_wake,
> +	.irq_set_type = tegra210_pmc_irq_set_type,
> +	.reset_sources = tegra210_reset_sources,
> +	.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
> +	.reset_levels = NULL,
> +	.num_reset_levels = 0,
> +	.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
> +	.wake_events = tegra210_wake_events,
> +	.pmc_clks_data = tegra_pmc_clks_data,
> +	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
> +	.has_blink_output = true,
> +	.has_usb_sleepwalk = true,
> +	.has_single_mmio_aperture = true,
> +};
> +
>  static const struct tegra_io_pad_soc tegra186_io_pads[] = {
>  	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"),
>  	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"),
> @@ -4824,6 +4885,7 @@ static const struct of_device_id tegra_pmc_match[] = {
>  	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
>  	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
>  	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
> +	{ .compatible = "nvidia,tegra210b01-pmc", .data = &tegra210b01_pmc_soc },
>  	{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
>  	{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
>  	{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
> 
> -- 
> 2.54.0
> 
> 
> 





  parent reply	other threads:[~2026-07-21  7:22 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-20  6:31 [PATCH v2 0/2] soc/tegra: pmc: Add Tegra210B01 support Aaron Kling via B4 Relay
2026-07-20  6:31 ` [PATCH v2 1/2] dt-bindings: soc: tegra: pmc: Document Tegra210B01 Aaron Kling via B4 Relay
2026-07-20 13:44   ` Rob Herring (Arm)
2026-07-20  6:31 ` [PATCH v2 2/2] soc/tegra: pmc: Add Tegra210B01 support Aaron Kling via B4 Relay
2026-07-20  6:45   ` sashiko-bot
2026-07-21  7:22   ` Mikko Perttunen [this message]
2026-07-21 17:42     ` Aaron Kling

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