Re: [PATCH v3 6/6] arm64: dts: cix: Describe the Sky1 DMA-350 bus integration

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: cix: missing memory-region for restricted AUDSS DMA
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commit bb152839bba0e4fcf17541cd1a7e5a05b3b33ae1
Author: Jelly Jia <Jelly.Jia@cixtech.com>

arm64: dts: cix: Describe the Sky1 DMA-350 bus integration

The FCH DMA-350 controller sits behind an interconnect window, so the
addresses its DMA master uses differ from the CPU physical addresses.
Describe the integration as a bus node carrying the dma-ranges of that
window, with the controller itself as a child, and give the controller
the SoC compatible and the clock feeding it.

> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index 0a820f45feb96..1262f34794d21 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi

[ ... ]

> @@ -576,6 +591,35 @@ mbox_pm2ap: mailbox@65a0080 {
>  			cix,mbox-dir = "rx";
>  		};
>  
> +		/*
> +		 * The AUDSS DMA-350 master sits behind an interconnect window;
> +		 * the dma-ranges below are its view of the address space.
> +		 */
> +		audss-dma-bus {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			dma-ranges = <0x0 0x20000000 0x0 0x07010000 0x0 0x00100000>,
> +				     <0x0 0x30000000 0x0 0xc0000000 0x0 0x20000000>;
> +
> +			audss_dmac: dma-controller@7010000 {
> +				compatible = "cix,sky1-dma350", "arm,dma-350";

[Severity: High]
Does this node need a memory-region property to provide a restricted DMA pool?

The AUDSS DMA-350 controller restricts its DRAM access to a 512MB window at
0xc0000000 via its parent's dma-ranges. Since system RAM normally starts at
0x80000000, default allocations for descriptors will fall outside this reachable
window.

When a driver calls generic routines to allocate and map these descriptors,
such as in drivers/dma/arm-dma350.c:d350_alloc_cmds():

    desc->cmds_dma = dma_map_single(dev, desc->cmds, desc->cmds_size,
                                    DMA_TO_DEVICE);
    if (dma_mapping_error(dev, desc->cmds_dma)) {

the mapping will fail because the generic allocation is out of bounds for this
device's DMA ranges. The global SWIOTLB bounce buffer would also be
inaccessible for the same reason.

> +				reg = <0x0 0x07010000 0x0 0x10000>;
> +				clocks = <&audss_cru CLK_DMAC_AXI>;
> +				resets = <&audss_cru AUDSS_DMAC_SW_RST>;

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Sashiko AI review · https://sashiko.dev/#/patchset/20261012084155.2547480-1-Jelly.Jia@cixtech.com?part=6