Devicetree
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From: sashiko-bot@kernel.org
To: "Petko Manolov" <petko.manolov@konsulko.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v9 3/3] arm: dts: altera: add Draeger M48 CPU Module
Date: Wed, 14 Oct 2026 13:23:26 +0000	[thread overview]
Message-ID: <sashiko-outbox-171346@kernel.org> (raw)
In-Reply-To: <20261014130228.2780803-4-petko.manolov@konsulko.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] dts: missing device_type = "memory" in memory node
- [Low] dt-bindings: missing PHY compatible string triggers dtbs_check warnings
--

commit d855694f7a7cff3fb10eeb71af859efb7af1158a
Author: Petko Manolov <petko.manolov@konsulko.com>

arm: dts: altera: add Draeger M48 CPU Module

This commit adds the device tree for the Altera SoCFPGA part of the
heterogeneous Draeger M48 board. The Cyclone V boots independently off
QSPI and monitors an i.MX6 CPU on the same module.

> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> new file mode 100644
> index 0000000000000..bc1909126e195
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  (C) Copyright 2020 Draeger and Licensors, info@draeger.com
> + */
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> +	model = "Draeger M48 Cyclone V SoC";
> +	compatible = "draeger,socfpga-m48", "altr,socfpga-cyclone5", "altr,socfpga";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@0 {
> +		reg = <0x0 0x40000000>;
> +	};

[Severity: Medium]
Should the memory@0 node include a device_type = "memory" property?

The Device Tree Specification mandates that memory nodes must include a
device_type = "memory" property. The kernel's early_init_dt_scan_memory()
explicitly checks for this property, and nodes lacking it are ignored.

While bootloaders like U-Boot often dynamically fix up or create the memory
node and its properties before passing the DT to the kernel, omitting it in
the source DTS is incorrect, triggers dtc and schema warnings, and could
lead to boot failure if the bootloader fails to inject the property.

[ ... ]

> +&gmac0 {
> +	status = "okay";
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy>;
> +
> +	mdio0 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +
> +		ethphy: ethernet-phy@0 {
> +			reg = <0>;
> +			rxc-skew-ps  = <1860>;
> +			rxd0-skew-ps = <0>;

[Severity: Low]
Could a compatible string be added to this PHY node?

The newly added ethernet PHY node uses vendor-specific skew properties
like rxc-skew-ps which are defined in micrel,gigabit.yaml. Because it
lacks a matching compatible string (such as ethernet-phy-id0022.1610),
the dt-schema validation tool does not apply the Micrel binding schema
to this node.

As a result, it falls back to the generic ethernet-phy.yaml schema, causing
dtbs_check to emit unevaluated property warnings for all the skew
properties. While the Linux kernel's MDIO bus will auto-detect the PHY ID
at runtime and apply the skews correctly via the Micrel driver, devicetree
validation requires the explicit compatible string.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261014130228.2780803-1-petko.manolov@konsulko.com?part=3

      reply	other threads:[~2026-10-14 13:23 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-14 13:02 [PATCH v9 0/3] arm: dts: altera: add Draeger M48 CPU board Petko Manolov
2026-10-14 13:02 ` [PATCH v9 1/3] dt-bindings: vendor-prefixes: add Draeger AG Petko Manolov
2026-10-14 13:02 ` [PATCH v9 2/3] dt-bindings: arm: altera: add Draeger M48 dual-cpu board Petko Manolov
2026-10-14 13:02 ` [PATCH v9 3/3] arm: dts: altera: add Draeger M48 CPU Module Petko Manolov
2026-10-14 13:23   ` sashiko-bot [this message]

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