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From: sashiko-bot@kernel.org
To: "Ali Rouhi" <arouhi@sitime.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH net-next v13 08/12] dpll: sit9531x: add support to get and set frequency on pins
Date: Wed, 14 Oct 2026 22:41:47 +0000	[thread overview]
Message-ID: <sashiko-outbox-171996@kernel.org> (raw)
In-Reply-To: <20261013224131.27149-9-arouhi@sitime.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dpll: sit9531x: byte order reversal when reading DIVN registers
--

commit f43a2163b7c3dc5944868b5794ea65a8398e4775
Author: Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>

dpll: sit9531x: add support to get and set frequency on pins

This commit adds the ability to get and set pin frequencies for the sit9531x
DPLL driver. It reads and writes DIVN registers to compute output frequency
based on VCO rate and a divider.

> diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c
> index f3dbe949f219b..875a5fe783d5c 100644
> --- a/drivers/dpll/sit9531x/core.c
> +++ b/drivers/dpll/sit9531x/core.c
[ ... ]
> @@ -1342,6 +1481,675 @@ int sit9531x_input_prio_add(struct sit9531x_dev *sitdev, u8 pll_idx,
[ ... ]
> +static int sit9531x_divn_static(struct sit9531x_dev *sitdev, u8 pll_idx,
> +				s64 *divn)
> +{
> +	u32 int_part, fracn_raw = 0, fracd_raw = 0;
> +	u64 fracd;
> +	s64 fracn;
> +	int rc, i;
> +	u8 v;
> +
> +	rc = sit9531x_read_pll_u8(sitdev, pll_idx,
> +				  SIT9531X_PLL_REG_DIVN_INT, &v);
> +	if (rc)
> +		return rc;
> +	int_part = v;
> +
> +	for (i = 3; i >= 0; i--) {
> +		rc = sit9531x_read_pll_u8(sitdev, pll_idx,
> +					  SIT9531X_PLL_REG_DIVN_NUM + i, &v);
> +		if (rc)
> +			return rc;
> +		fracn_raw = (fracn_raw << 8) | v;
> +	}

[Severity: Medium]
Since the device registers are big-endian, does this loop reverse the byte
order? By looping i from 3 down to 0 and shifting the result left, the
value from the highest address (which should be the LSB) is placed into
the most significant byte of fracn_raw, which could result in incorrect
VCO frequency calculations.

> +
> +	for (i = 3; i >= 0; i--) {
> +		rc = sit9531x_read_pll_u8(sitdev, pll_idx,
> +					  SIT9531X_PLL_REG_DIVN_DEN + i, &v);
> +		if (rc)
> +			return rc;
> +		fracd_raw = (fracd_raw << 8) | v;
> +	}

[Severity: Medium]
Similarly for the denominator, is the byte order also reversed here by
reading the highest address first and shifting it into the MSB?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261013224131.27149-1-arouhi@sitime.com?part=8

  reply	other threads:[~2026-10-14 22:41 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-13 22:41 [PATCH net-next v13 00/12] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 01/12] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 03/12] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-10-14 22:41   ` sashiko-bot
2026-10-13 22:41 ` [PATCH net-next v13 04/12] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-10-14 22:41   ` sashiko-bot
2026-10-13 22:41 ` [PATCH net-next v13 05/12] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-10-14 22:41   ` sashiko-bot
2026-10-13 22:41 ` [PATCH net-next v13 06/12] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 07/12] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 08/12] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-10-14 22:41   ` sashiko-bot [this message]
2026-10-13 22:41 ` [PATCH net-next v13 09/12] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 10/12] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-10-14 22:41   ` sashiko-bot
2026-10-13 22:41 ` [PATCH net-next v13 11/12] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-10-13 22:41 ` [PATCH net-next v13 12/12] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
2026-10-14 22:41   ` sashiko-bot

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