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From: sashiko-bot@kernel.org
To: "Mohammad Rafi Shaik" <mohammad.rafi.shaik@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v1 2/4] ASoC: codecs: pm4125: Fix MBHC button threshold programming
Date: Thu, 15 Oct 2026 14:27:59 +0000	[thread overview]
Message-ID: <sashiko-outbox-172959@kernel.org> (raw)
In-Reply-To: <20261015-pm4125_mbhc_support-v1-2-8bc1212db6f7@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] pm4125: out-of-bounds register write in pm4125_mbhc_program_btn_thr()
--

commit 2cce30fa45a4f0c5ff81fb48ecba9f5d3b9f5681
Author: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>

ASoC: codecs: pm4125: Fix MBHC button threshold programming

This commit fixes MBHC button threshold programming by removing an
incorrect double shift of the threshold value before passing it to
snd_soc_component_write_field().

> diff --git a/sound/soc/codecs/pm4125.c b/sound/soc/codecs/pm4125.c
> index 674a2fbc4edae..923318c78d261 100644
> --- a/sound/soc/codecs/pm4125.c
> +++ b/sound/soc/codecs/pm4125.c
> @@ -981,7 +981,7 @@ static void pm4125_mbhc_program_btn_thr(struct snd_soc_component *component,
>  	for (i = 0; i < num_btn; i++) {
>  		vth = ((btn_high[i] * 2) / 25) & 0x3F;
>  		snd_soc_component_write_field(component, PM4125_ANA_MBHC_BTN0_ZDET_VREF1 + i,
> -					      PM4125_ANA_MBHC_BTN0_THRESHOLD_MASK, vth << 2);
> +					      PM4125_ANA_MBHC_BTN0_THRESHOLD_MASK, vth);

[Severity: High]
Does this code write past the end of the button threshold registers?

The pm4125_probe() function sets cfg->num_btn = PM4125_MBHC_MAX_BUTTONS
(which is defined as 8). However, the PM4125 codec only has 5 button
threshold registers:

sound/soc/codecs/pm4125.h:
#define PM4125_ANA_MBHC_BTN0_ZDET_VREF1         (PM4125_ANA_BASE_ADDR+0x060)
...
#define PM4125_ANA_MBHC_BTN4_ZDET_DBG_1400      (PM4125_ANA_BASE_ADDR+0x064)
#define PM4125_ANA_MBHC_MICB2_RAMP              (PM4125_ANA_BASE_ADDR+0x065)
#define PM4125_ANA_MBHC_CTL_1                   (PM4125_ANA_BASE_ADDR+0x066)

Because the loop iterates 8 times, it writes threshold voltages into offsets
0x065, 0x066, and 0x067. Can this silently corrupt the adjacent
PM4125_ANA_MBHC_MICB2_RAMP, PM4125_ANA_MBHC_CTL_1, and
PM4125_ANA_MBHC_CTL_2 registers?

>  	}
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261015-pm4125_mbhc_support-v1-0-8bc1212db6f7@oss.qualcomm.com?part=2

  reply	other threads:[~2026-10-15 14:28 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-15 14:13 [PATCH 0/4] ASoC: codecs: pm4125: Enable MBHC jack detection Mohammad Rafi Shaik
2026-10-15 14:13 ` [PATCH v1 1/4] ASoC: dt-bindings: qcom,pm4125-codec: Add the MBHC jack properties Mohammad Rafi Shaik
2026-10-15 14:13 ` [PATCH v1 2/4] ASoC: codecs: pm4125: Fix MBHC button threshold programming Mohammad Rafi Shaik
2026-10-15 14:27   ` sashiko-bot [this message]
2026-10-15 14:13 ` [PATCH v1 3/4] ASoC: codecs: pm4125: Keep the micbias reference count balanced Mohammad Rafi Shaik
2026-10-15 14:25   ` sashiko-bot
2026-10-15 19:03   ` Mark Brown
2026-10-15 14:13 ` [PATCH v1 4/4] ASoC: codecs: pm4125: Add the MBHC callbacks needed for jack detection Mohammad Rafi Shaik
2026-10-15 14:27   ` sashiko-bot

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