Re: [PATCH v10 04/10] clk: nuvoton: ma35d1: Reparent the gates correctly

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: nuvoton: CCAP muxes registered with 1-bit width but 4 parents
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commit eafc7cdaf7d2454016081e967de0730635be9342
Author: Miquel Raynal <miquel.raynal@bootlin.com>

clk: nuvoton: ma35d1: Reparent the gates correctly

The clock tree is still incorrect. There are four main clocks in this
system: HXT, LXT, HIRC, LIRC. Each clock has a gate control to disable
it, and in the CCF topology, the gates should be below the clocks so
children stop ticking when gated. This commit reparents the gates under
their respective sources and all children under the gates.

> diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c
> index 33b397d7b7c52..65a2691002a73 100644
> --- a/drivers/clk/nuvoton/clk-ma35d1.c
> +++ b/drivers/clk/nuvoton/clk-ma35d1.c
> @@ -74,34 +74,46 @@ static const struct clk_parent_data lxtg_parent_data[] = {
[ ... ]
>  static const int axiclk_parent_idx[] = { AXICLK_DIV2, AXICLK_DIV4 };
> -static const int ccap_parent_idx[] = { HXT, VPLL, APLL, SYSPLL };
> +static const int ccap_parent_idx[] = { HXT_GATE, VPLL, APLL, SYSPLL };

[Severity: Medium]
The ccap_parent_idx array defines 4 parent clocks (HXT_GATE, VPLL, APLL, SYSPLL).
However, CCAP0_MUX and CCAP1_MUX are registered with ma35d1_clk_mux()
using a 1-bit width:

drivers/clk/nuvoton/clk-ma35d1.c:ma35d1_clocks_probe() {
    ...
    hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0, 12, 1, hws,
                                    ccap_parent_idx, ARRAY_SIZE(ccap_parent_idx));
    ...
}

Since a 1-bit hardware mux field can only address 2 parents (indices 0 and 1),
will attempting to select APLL or SYSPLL result in truncation of the parent
index or a framework error, rendering those parents unusable?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261015-perso-ma35d1-upstream-clk-v10-0-47c97b54a809@bootlin.com?part=4