Re: [PATCH v5 8/8] irqchip/realtek-rtd1625: Add driver for Realtek DHC rtd1625 SoC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] irqchip/realtek-rtd1625: ISOM GPIOA bit 0 status masked out by CLEAN_INTC_STATUS
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commit b2c8018866210ca4432e6b3019fc9b2e2b7b080d
Author: James Tai <james.tai@realtek.com>

irqchip/realtek-rtd1625: Add driver for Realtek DHC rtd1625 SoC

This commit adds support for the ISO, ISOM, and MISC interrupt controllers on
Realtek DHC RTD1625 SoCs using the common Realtek DHC interrupt controller
framework.

> diff --git a/drivers/irqchip/irq-realtek-rtd1625.c b/drivers/irqchip/irq-realtek-rtd1625.c
> new file mode 100644
> index 0000000000000..4cca66c8ff701
> --- /dev/null
> +++ b/drivers/irqchip/irq-realtek-rtd1625.c

[ ... ]

> +enum rtd1625_isom_isr_bits {
> +	RTD1625_ISOM_ISR_GPIOA_SHIFT		= 0,
> +	RTD1625_ISOM_ISR_GPIODA_SHIFT		= 1,
> +	RTD1625_ISOM_ISR_GPIO_LEVEL_SHIFT	= 2,
> +	RTD1625_ISOM_ISR_UR10_SHIFT		= 4,
> +	RTD1625_ISOM_ISR_IRDA_SHIFT		= 5,
> +};
> +
> +static const u32 rtd1625_isom_isr_to_scpu_int_en_mask[32] = {
> +	[RTD1625_ISOM_ISR_GPIOA_SHIFT]		= BIT(0),
> +	[RTD1625_ISOM_ISR_GPIODA_SHIFT]		= BIT(1),
> +	[RTD1625_ISOM_ISR_GPIO_LEVEL_SHIFT]	= BIT(2),
> +	[RTD1625_ISOM_ISR_UR10_SHIFT]		= BIT(4),
> +	[RTD1625_ISOM_ISR_IRDA_SHIFT]		= BIT(5),
> +};

[Severity: High]
Can the status bit for RTD1625_ISOM_ISR_GPIOA_SHIFT (bit 0) ever be cleared
when an interrupt fires or during suspend and resume?

In drivers/irqchip/irq-realtek-intc-common.h, CLEAN_INTC_STATUS excludes
bit 0:

    #define CLEAN_INTC_STATUS	GENMASK(31, 1)

When bit 0 of ISOM_ISR is set (which is included in ISOM_NORMAL_MASK
0x00000037), realtek_intc_dispatch() in
drivers/irqchip/irq-realtek-intc-common.c handles irq 0 and then attempts to
clear the status register:

    while (ints) {
        irq = __ffs(ints);
        ...
        regmap_write(data->base, bank_info->isr_offset, BIT(irq) & CLEAN_INTC_STATUS);
    }

Because BIT(0) & CLEAN_INTC_STATUS evaluates to 0, regmap_write() writes 0
instead of BIT(0), leaving the interrupt status bit asserted and causing an
interrupt storm. Similarly, realtek_intc_suspend() and realtek_intc_resume()
write CLEAN_INTC_STATUS to info->isr_offset, which also leaves bit 0
uncleared.

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20261018160653.3940371-1-eleanor.lin@realtek.com?part=8