From: sashiko-bot@kernel.org
To: "Svyatoslav Ryhel" <clamor95@gmail.com>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 2/7] drm/tegra: rgb: Parameterize configuration based on bus flags
Date: Mon, 19 Oct 2026 10:15:47 +0000 [thread overview]
Message-ID: <sashiko-outbox-176969@kernel.org> (raw)
In-Reply-To: <20261019095705.91062-3-clamor95@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/tegra: rgb: unlocked drm_bridge_get_current_state() in encoder enable
--
commit 62888cceae72e28c0425a5560b48d0bf56dccc9e
Author: Svyatoslav Ryhel <clamor95@gmail.com>
drm/tegra: rgb: Parameterize configuration based on bus flags
This commit parameterizes the Tegra RGB encoder configuration based on bus
flags from the bridge state, including pixel clock polarity, display enable
polarity, and data alignment.
> diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
> index b6d09a8d8e5ea..da9e37fe36689 100644
> --- a/drivers/gpu/drm/tegra/rgb.c
> +++ b/drivers/gpu/drm/tegra/rgb.c
[ ... ]
> @@ -104,14 +105,24 @@ static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
> struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
> struct tegra_output *output = encoder_to_output(encoder);
> struct tegra_rgb *rgb = to_rgb(output);
> - u32 value;
> + struct drm_bridge_state *bridge_state;
> + u32 bus_flags, value;
> +
> + /* Get but flags from the bridge state. */
> + bridge_state = drm_bridge_get_current_state(output->bridge);
> + if (bridge_state)
> + bus_flags = bridge_state->input_bus_cfg.flags;
> + else
> + bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
> + DRM_BUS_FLAG_DE_HIGH |
> + DRM_BUS_FLAG_DATA_MSB_TO_LSB;
[Severity: High]
Is it safe to call drm_bridge_get_current_state() from
tegra_rgb_encoder_enable()?
Looking at include/drm/drm_bridge.h, drm_bridge_get_current_state() asserts
that bridge->base.lock is held:
static inline struct drm_bridge_state *
drm_bridge_get_current_state(struct drm_bridge *bridge)
{
if (!bridge)
return NULL;
drm_modeset_lock_assert_held(&bridge->base.lock);
if (!bridge->base.state)
return NULL;
return drm_priv_to_bridge_state(bridge->base.state);
}
When userspace submits a non-blocking atomic modeset commit
(DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET),
drm_atomic_helper_commit() swaps the state and schedules commit_work on
system_dfl_wq, after which drm_mode_atomic_ioctl() drops all modeset locks.
The worker thread then executes without holding bridge->base.lock:
commit_work() ->
commit_tail() ->
tegra_atomic_commit_tail() ->
drm_atomic_helper_commit_tail_rpm() ->
drm_atomic_helper_commit_modeset_enables() ->
drm_atomic_helper_commit_encoder_bridge_enable() ->
tegra_rgb_encoder_enable()
Won't calling drm_bridge_get_current_state(output->bridge) here trigger a
lockdep warning when CONFIG_PROVE_LOCKING is enabled and read
bridge->base.state without synchronization against concurrent atomic state
swaps?
Should this encoder implement .atomic_enable and retrieve the bridge state via
drm_atomic_get_new_bridge_state(state, output->bridge), or cache bus_flags
during .atomic_check instead?
[ ... ]
>
> tegra_dc_commit(rgb->dc);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261019095705.91062-1-clamor95@gmail.com?part=2
next prev parent reply other threads:[~2026-10-19 10:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-19 9:56 [PATCH v3 0/7] drm/tegra: Add support for Tegra20/Tegra30 8-bit CPU interface Svyatoslav Ryhel
2026-10-19 9:56 ` [PATCH v3 1/7] drm/tegra: dc: Expand available registers layouts Svyatoslav Ryhel
2026-10-19 9:57 ` [PATCH v3 2/7] drm/tegra: rgb: Parameterize configuration based on bus flags Svyatoslav Ryhel
2026-10-19 10:15 ` sashiko-bot [this message]
2026-10-19 9:57 ` [PATCH v3 3/7] dt-bindings: display: tegra: Document 8-bit CPU parallel interface Svyatoslav Ryhel
2026-10-19 10:09 ` sashiko-bot
2026-10-20 15:12 ` Rob Herring (Arm)
2026-10-19 9:57 ` [PATCH v3 4/7] drm/tegra: Add support for 8-bit CPU interface Svyatoslav Ryhel
2026-10-19 10:20 ` sashiko-bot
2026-10-19 9:57 ` [PATCH v3 5/7] dt-bindings: display: panel: Document Hitachi TX10D07VM0BAA and LG LH400WV3 panels Svyatoslav Ryhel
2026-10-19 9:57 ` [PATCH v3 6/7] drm/panel: Add Hitachi TX10D07VM0BAA MIPI DBI Type B panel driver Svyatoslav Ryhel
2026-10-19 10:09 ` sashiko-bot
2026-10-19 9:57 ` [PATCH v3 7/7] drm/panel: Add LG LH400WV3-SD04 " Svyatoslav Ryhel
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