Re: [PATCH v3 05/14] drm/solomon: ssd16xx: Add clear_on_init/close/disable session management

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] drm/solomon: ssd16xx: wrong RAM window in ssd16xx_clear_display() for 90/180
- [High] drm/solomon: ssd16xx: ssd16xx_clear_display() breaks partial refresh protocol
- [High] drm/solomon: ssd16xx: missing fast LUT preload in ssd16xx_clear_display()
- [High] drm/solomon: ssd16xx: clear_on_init skipped when CRTC is already enabled
- [Medium] drm/solomon: ssd16xx: split clear flags fail to prevent double clear on exit
--

commit 3af87653bdf02bc80f3063d4c3e270de771de868
Author: Devarsh Thakkar <devarsht@ti.com>

drm/solomon: ssd16xx: Add clear_on_init/close/disable session management

This commit adds session-lifetime display clearing for SSD16xx e-paper panels
via three configurable hooks: clear_on_init, clear_on_close, and
clear_on_disable. Each hook selects the refresh waveform to use when blanking
the display and defaults to -1 (disabled).

> diff --git a/drivers/gpu/drm/solomon/ssd16xx.c b/drivers/gpu/drm/solomon/ssd16xx.c
> index ca6550b5dd5bd..7b00964487681 100644
> --- a/drivers/gpu/drm/solomon/ssd16xx.c
> +++ b/drivers/gpu/drm/solomon/ssd16xx.c

[ ... ]

> @@ -754,6 +775,138 @@ static int ssd16xx_hw_init(struct ssd16xx_device *device)
>  	return err;
>  }
>  
> +/*
> + * Clear display by writing all-white to both BW and RED RAM.
> + * The ctrl2 argument selects the waveform (full/partial/fast refresh).
> + * Border waveform is set to init value before clearing, then restored
> + * to the update value to preserve the border during subsequent updates.
> + */
> +static int ssd16xx_clear_display(struct ssd16xx_device *device, u8 ctrl2)
> +{
> +	const u8 *bw_tbl = device->controller_cfg->border_waveform_table;
> +	int err = 0;
> +	unsigned int data_size = DIV_ROUND_UP(device->width, 8) * device->height;
> +	u8 *white_buffer = device->tx_buf;
> +	u8 *red_buffer = white_buffer;
> +	u16 ram_x_end, ram_y_end;
> +
> +	memset(white_buffer, 0xFF, data_size);
> +
> +	if (device->controller_cfg->ram_x_address_bits == 8)
> +		ram_x_end = (device->width / 8) - 1;
> +	else
> +		ram_x_end = device->width - 1;
> +	ram_y_end = device->height - 1;
> +
> +	/* Reset full display RAM window before clearing */
> +	ssd16xx_send_cmd(device, SSD16XX_CMD_SET_RAM_X_ADDRESS_START_END, &err);
> +	ssd16xx_send_x_param(device, 0x00, &err);
> +	ssd16xx_send_x_param(device, ram_x_end, &err);
> +
> +	ssd16xx_send_cmd(device, SSD16XX_CMD_SET_RAM_Y_ADDRESS_START_END, &err);
> +	ssd16xx_send_y_param(device, 0x00, &err);
> +	ssd16xx_send_y_param(device, ram_y_end, &err);
> +
> +	ssd16xx_send_cmd(device, SSD16XX_CMD_SET_RAM_X_ADDRESS_COUNTER, &err);
> +	ssd16xx_send_x_param(device, 0x00, &err);
> +
> +	ssd16xx_send_cmd(device, SSD16XX_CMD_SET_RAM_Y_ADDRESS_COUNTER, &err);
> +	ssd16xx_send_y_param(device, 0x00, &err);

[Severity: High]
When device->orientation is 90 or 180 degrees, ssd16xx_hw_init() sets
SSD16XX_CMD_DATA_ENTRY_MODE to SSD16XX_DATA_ENTRY_XDEC_YDEC:

drivers/gpu/drm/solomon/ssd16xx.c:ssd16xx_hw_init() {
	switch (device->orientation) {
	case 90:
	case 180:
		data_entry_mode = SSD16XX_DATA_ENTRY_XDEC_YDEC;
		break;
	default: /* 0°/270° */
		data_entry_mode = SSD16XX_DATA_ENTRY_XINC_YINC;
		break;
	}

	ssd16xx_send_cmd(device, SSD16XX_CMD_DATA_ENTRY_MODE, &err);
	ssd16xx_send_data(device, data_entry_mode, &err);
}

In ssd16xx_fb_dirty(), 90 and 180 degree orientations program the RAM window
in end-before-start order and set the initial cursor to (ram_x_end,
ram_y_end):

drivers/gpu/drm/solomon/ssd16xx.c:ssd16xx_fb_dirty() {
	switch (device->orientation) {
	case 90:
	case 180:
		/* 90°/180°: XDEC_YDEC mode, send end-before-start; cursor at (max, max). */
		ssd16xx_send_cmd(device, SSD16XX_CMD_SET_RAM_X_ADDRESS_START_END, &err);
		ssd16xx_send_x_param(device, ram_x_end, &err);
		ssd16xx_send_x_param(device, ram_x_start, &err);
		...
}

Since ssd16xx_clear_display() always programs start=0x00, end=ram_x_end/
ram_y_end and sets the address counters to (0x00, 0x00) without switching
SSD16XX_CMD_DATA_ENTRY_MODE or checking device->orientation, will bulk writes
to SSD16XX_CMD_WRITE_RAM_BW and SSD1683_CMD_WRITE_RAM_RED fail to traverse
and clear the display RAM when the panel is rotated 90 or 180 degrees?

> +
> +	ssd16xx_send_cmd(device, SSD16XX_CMD_WRITE_RAM_BW, &err);
> +	ssd16xx_send_data_bulk(device, white_buffer, data_size, &err);
> +
> +	/*
> +	 * In 3-colour mode RED RAM is the red plane, so clear it to 0x00 (no
> +	 * red).  Otherwise it is the previous-frame reference for partial
> +	 * refresh and must match the now all-white BW RAM.
> +	 */
> +	if (device->color_mode == SSD16XX_COLOR_MODE_3COLOR && device->tx_red_buf) {
> +		red_buffer = device->tx_red_buf;
> +		memset(red_buffer, 0x00, data_size);
> +	}
> +
> +	ssd16xx_send_cmd(device, SSD1683_CMD_WRITE_RAM_RED, &err);
> +	ssd16xx_send_data_bulk(device, red_buffer, data_size, &err);
> +
> +	/* Set border waveform for the clear operation */
> +	drm_dbg(&device->drm, "clear_display: Set border init waveform: 0x%02x\n",
> +		bw_tbl[device->border_waveform_init_idx]);
> +	ssd16xx_send_cmd(device, SSD16XX_CMD_BORDER_WAVEFORM_CONTROL, &err);
> +	ssd16xx_send_data(device,
> +			  bw_tbl[device->border_waveform_init_idx],
> +			  &err);
> +
> +	/* 3-colour mode: CTRL1_NORMAL (read both RAMs); BW mode: bypass RED. */
> +	ssd16xx_display_update(device,
> +			       device->color_mode == SSD16XX_COLOR_MODE_3COLOR
> +					? device->controller_cfg->ctrl1_normal
> +					: device->controller_cfg->ctrl1_bypass_red_ram,
> +			       SSD16XX_CTRL1_BYTE2_DEFAULT, ctrl2, &err);

[Severity: High]
How does ssd16xx_clear_display() work when any of clear_on_init,
clear_on_close, or clear_on_disable is set to 0 (SSD16XX_REFRESH_PARTIAL)?

In ssd16xx_fb_dirty(), partial refresh uses ctrl1_normal so the controller
compares BW RAM (new frame) against RED RAM (previous frame), and writes the
new frame to RED RAM only after ssd16xx_display_update() completes:

drivers/gpu/drm/solomon/ssd16xx.c:ssd16xx_fb_dirty() {
	case SSD16XX_REFRESH_PARTIAL:
	default:
		ssd16xx_display_update(device, device->controller_cfg->ctrl1_normal,
				       SSD16XX_CTRL1_BYTE2_DEFAULT,
				       ctrl2_tbl[SSD16XX_REFRESH_PARTIAL], &err);
		ssd16xx_send_cmd(device, SSD1683_CMD_WRITE_RAM_RED, &err);
		ssd16xx_send_data_bulk(device, mono_buffer, data_size, &err);
		break;
}

Here in ssd16xx_clear_display(), RED RAM is overwritten with white_buffer
before ssd16xx_display_update(), and in BW mode ctrl1_bypass_red_ram is
passed instead of ctrl1_normal. Doesn't overwriting and bypassing RED RAM
before the update prevent the partial refresh waveform from driving
previously black pixels to white?

[Severity: High]
What happens if clear_on_init, clear_on_close, or clear_on_disable is set to
2 (SSD16XX_REFRESH_FAST) while device->refresh_mode is
SSD16XX_REFRESH_PARTIAL (the default for GDEY042T81)?

In ssd16xx_hw_init(), the fast refresh LUT is only preloaded when
device->refresh_mode == SSD16XX_REFRESH_FAST:

drivers/gpu/drm/solomon/ssd16xx.c:ssd16xx_hw_init() {
	if (device->refresh_mode == SSD16XX_REFRESH_FAST) {
		ssd16xx_send_cmd(device, SSD16XX_CMD_DISPLAY_UPDATE_CONTROL1, &err);
		ssd16xx_send_data(device, device->controller_cfg->ctrl1_bypass_red_ram, &err);
		ssd16xx_send_data(device, SSD16XX_CTRL1_BYTE2_DEFAULT, &err);

		ssd16xx_send_cmd(device, SSD16XX_CMD_DISPLAY_UPDATE_CONTROL2, &err);
		ssd16xx_send_data(device, device->controller_cfg->ctrl2_load_temp_lut, &err);

		ssd16xx_send_cmd(device, SSD16XX_CMD_MASTER_ACTIVATION, &err);
		ssd16xx_wait_for_device(device, &err);
	}
}

Because SSD1683_CTRL2_FAST_REFRESH (0xC7) omits SSD16XX_CTRL2_LOAD_LUT, won't
calling ssd16xx_clear_display() with fast refresh run with no LUT loaded on
init (after SW_RESET in ssd16xx_hw_init()) or with the Mode 2 partial LUT on
disable/close (after partial refreshes)? Conversely, if device->refresh_mode
is SSD16XX_REFRESH_FAST and a partial clear runs, won't the partial clear
overwrite the hardware LUT with Mode 2 without setting
device->fast_lut_pending?

[ ... ]

> @@ -1388,6 +1568,12 @@ static void ssd16xx_crtc_atomic_enable(struct drm_crtc *crtc,
>  		}
>  		device->initialized = true;
>  	}
> +	device->cleared_on_disable = false;
> +
> +	/* Clear display on first app launch if configured */
> +	ret = ssd16xx_clear_display_on_init(device);
> +	if (ret)
> +		drm_err(&device->drm, "crtc_atomic_enable: clear on init failed: %d\n", ret);
>  
>  	/*
>  	 * If refresh_mode_init is set, arm init_refresh_pending so

[ ... ]

> @@ -1473,6 +1660,9 @@ static void ssd16xx_drm_master_set(struct drm_device *drm,
>  {
>  	struct ssd16xx_device *device = to_ssd16xx_device(drm);
>  
> +	device->cleared_on_close = false;
> +	device->first_clear_done = false;
> +
>  	if (device->refresh_mode_init >= 0)
>  		device->init_refresh_pending = true;
>  }

[Severity: High]
In ssd16xx_drm_master_set(), device->first_clear_done is reset to false so a
new DRM master session gets a fresh clear. However,
ssd16xx_clear_display_on_init() is only called from
ssd16xx_crtc_atomic_enable().

If the CRTC is already enabled in the panel's single fixed mode (for example,
by fbdev emulation or because the previous client exited without disabling
the CRTC), a new DRM master committing a framebuffer update will only run
ssd16xx_plane_atomic_update() without triggering a modeset or calling
ssd16xx_crtc_atomic_enable().

Will clear_on_init be skipped entirely for the new DRM master whenever the
CRTC is already active?

> @@ -1485,8 +1675,23 @@ static void ssd16xx_drm_master_drop(struct drm_device *drm,
>  				    struct drm_file *file)
>  {
>  	struct ssd16xx_device *device = to_ssd16xx_device(drm);
> +	int ret, idx;
>  
>  	device->init_refresh_pending = false;
> +	device->first_clear_done = false;
> +
> +	if (device->clear_on_close < 0 || device->cleared_on_close)
> +		return;
> +
> +	if (!drm_dev_enter(drm, &idx))
> +		return;
> +
> +	ret = ssd16xx_clear_display_on_exit(device);
> +	if (ret)
> +		drm_err(drm, "master_drop: clear on close failed: %d\n", ret);
> +
> +	device->cleared_on_close = true;
> +	drm_dev_exit(idx);
>  }

[Severity: Medium]
The commit message notes that a guard prevents redundant double-clears when
multiple paths fire for the same session (such as when a compositor does DPMS
off and then exits).

In ssd16xx_crtc_atomic_disable(), disabling the CRTC sets
device->cleared_on_disable = true:

drivers/gpu/drm/solomon/ssd16xx.c:ssd16xx_crtc_atomic_disable() {
	if (device->clear_on_disable < 0 || device->cleared_on_disable)
		goto out;
	...
	device->cleared_on_disable = true;
}

However, ssd16xx_drm_master_drop() only checks device->cleared_on_close and
does not check device->cleared_on_disable. When both clear_on_disable and
clear_on_close are enabled and a client disables the CRTC (or closes its fd
while its framebuffer is active on the CRTC, which disables the CRTC via
drm_fb_release() before drm_master_release()), won't both
ssd16xx_crtc_atomic_disable() and ssd16xx_drm_master_drop() execute a full
clear cycle back-to-back?

>  
>  static struct drm_driver ssd16xx_drm_driver = {

[ ... ]

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-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261019213726.4145532-1-devarsht@ti.com?part=5