Re: [PATCH v3 2/3] ARM: dts: aspeed: add Intel AVCRP BMC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] ARM: dts: aspeed: avcrp: pinmux conflicts on uart3, uart4, and gpio0
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commit 01d3c06dda0485c95a5f1bf0fb7cf7492e56bdd4
Author: Dawid Glazik <dawid.glazik@linux.intel.com>

ARM: dts: aspeed: add Intel AVCRP BMC

This commit adds the initial device tree for the Intel AVCRP BMC platform
based on the Aspeed AST2600 SoC.

> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-avcrp.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-avcrp.dts
> new file mode 100644
> index 0000000000000..010ace09d90ff
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-avcrp.dts
> @@ -0,0 +1,322 @@

[ ... ]

> +&gpio0 {
> +	gpio-line-names =
> +		/*A0-A7*/ "", "", "", "", "SMB_CPU_PIROM_SCL", "SMB_CPU_PIROM_SDA",
> +				"SMB_IPMB_STBY_LVC3_SCL", "SMB_IPMB_STBY_LVC3_SDA",
> +		/*B0-B7*/ "", "", "", "FM_CPU1_ERR2_LVT3_N", "", "",
> +				"FM_BMC_BMCINIT_R", "FP_ID_LED_N",

[ ... ]

> +		/*L0-L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "",
> +		/*M0-M7*/ "", "", "", "", "", "", "SPA_SOUT", "SPA_SIN",

[ ... ]

> +};

[ ... ]

> +&uart1 {
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	status = "okay";
> +};

[Severity: Medium]
Should &uart3 and &uart4 override pinctrl-0 = <>; here, and should the
pinctrl-claimed pins in &gpio0 be cleared from gpio-line-names?

In arch/arm/boot/dts/aspeed/aspeed-g6.dtsi, uart3 and uart4 default to
pinctrl_txd3_default / pinctrl_rxd3_default (pins L4 and L5) and
pinctrl_txd4_default / pinctrl_rxd4_default (pins B6 and B7). In &gpio0
above, those pins are named as board lines PREQ_N, TCK_MUX_SEL,
FM_BMC_BMCINIT_R, and FP_ID_LED_N.

Because aspeed_g6_pinmux_ops in drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
sets .strict = true, probing &uart3 and &uart4 claims exclusive mux
ownership of L4-L5 and B6-B7 via pin_request() in drivers/pinctrl/pinmux.c.
This muxes those balls to TXD3/RXD3 and TXD4/RXD4 and causes any subsequent
request for those lines via aspeed_gpio_request() -> pinctrl_gpio_request()
to fail with -EINVAL.

Also, in &gpio0, pins A4-A7 (SMB_CPU_PIROM_SCL, SMB_CPU_PIROM_SDA,
SMB_IPMB_STBY_LVC3_SCL, SMB_IPMB_STBY_LVC3_SDA) and M6-M7 (SPA_SOUT,
SPA_SIN) still have gpio-line-names entries even though they are claimed by
&i2c12 (pinctrl_i2c13_default), &i2c13 (pinctrl_i2c14_default), and &uart1
(pinctrl_txd1_default / pinctrl_rxd1_default).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1792613583.git.dawid.glazik@linux.intel.com?part=2