Devicetree
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From: sashiko-bot@kernel.org
To: "Xincheng Ji" <jixincheng@ultrarisc.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v5 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
Date: Fri, 23 Oct 2026 02:10:15 +0000	[thread overview]
Message-ID: <sashiko-outbox-182213@kernel.org> (raw)
In-Reply-To: <20261023-ultrarisc-dts-v5-5-af79dbd6ccec@ultrarisc.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] riscv: dts: ultrarisc: use interrupt-controller node name for plic
--

commit 1a3ff8774c13bffe4745b26609b00045901e6bc4
Author: Jia Wang <wangjia@ultrarisc.com>

riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000

This commit adds the base device tree for the UltraRISC DP1000 SoC,
describing its eight CP100 CPU cores, cache topology, and core peripherals.

> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
> new file mode 100644
> index 0000000000000..220e000a16989
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
> @@ -0,0 +1,865 @@

[ ... ]

> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		clint: clint@8000000 {
> +			compatible = "ultrarisc,dp1000-clint", "sifive,clint0";
> +			reg = <0x0 0x8000000 0x0 0x100000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> +					      <&cpu3_intc 3>, <&cpu3_intc 7>,
> +					      <&cpu4_intc 3>, <&cpu4_intc 7>,
> +					      <&cpu5_intc 3>, <&cpu5_intc 7>,
> +					      <&cpu6_intc 3>, <&cpu6_intc 7>,
> +					      <&cpu7_intc 3>, <&cpu7_intc 7>;
> +		};
> +
> +		plic: plic@9000000 {
> +			compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic";
> +			reg = <0x0 0x9000000 0x0 0x4000000>;
> +			#interrupt-cells = <1>;
> +			#address-cells = <0>;
> +			interrupt-controller;

[Severity: Low]
Should the plic node in arch/riscv/boot/dts/ultrarisc/dp1000.dtsi be named
interrupt-controller@9000000 instead of plic@9000000?

Because this node has the interrupt-controller property, dtschema's
interrupt-controller.yaml and
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
require the node name to match interrupt-controller@<addr>, otherwise running
dtbs_check on boards including dp1000.dtsi will report a nodename validation
warning.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261023-ultrarisc-dts-v5-0-af79dbd6ccec@ultrarisc.com?part=5

  reply	other threads:[~2026-10-23  2:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-23  1:56 [PATCH v5 0/7] riscv: Add device tree support for UltraRISC DP1000 Xincheng Ji via B4 Relay
2026-10-23  1:56 ` [PATCH v5 1/7] dt-bindings: vendor-prefixes: Add shenrongda Xincheng Ji via B4 Relay
2026-10-23  1:56 ` [PATCH v5 2/7] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Xincheng Ji via B4 Relay
2026-10-23  1:56 ` [PATCH v5 3/7] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Xincheng Ji via B4 Relay
2026-10-23  1:56 ` [PATCH v5 4/7] dt-bindings: timer: Add UltraRISC DP1000 CLINT Xincheng Ji via B4 Relay
2026-10-23  1:56 ` [PATCH v5 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Xincheng Ji via B4 Relay
2026-10-23  2:10   ` sashiko-bot [this message]
2026-10-23  8:04     ` Xincheng Ji
2026-10-23  1:56 ` [PATCH v5 6/7] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Xincheng Ji via B4 Relay
2026-10-23  1:56 ` [PATCH v5 7/7] riscv: dts: ultrarisc: Add Milk-V Titan " Xincheng Ji via B4 Relay

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