From: sashiko-bot@kernel.org
To: "Xincheng Ji" <jixincheng@ultrarisc.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v6 7/7] riscv: dts: ultrarisc: Add Milk-V Titan board device tree
Date: Sat, 24 Oct 2026 09:50:12 +0000 [thread overview]
Message-ID: <sashiko-outbox-183632@kernel.org> (raw)
In-Reply-To: <20261024-ultrarisc-dts-v6-7-c62994d8a114@ultrarisc.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] riscv: dts: ultrarisc: malformed PLIC node name breaks DTB build
- [Low] riscv: dts: ultrarisc: unrelated dp1000-shenrongda-m0.dts fixup
--
commit 81481b50c1512c545051667e9b53f021c85ecb18
Author: Jia Wang <wangjia@ultrarisc.com>
riscv: dts: ultrarisc: Add Milk-V Titan board device tree
This commit adds the device tree and pinctrl definitions for the Milk-V
Titan ITX motherboard based on the UltraRISC DP1000 SoC.
Link: https://milkv.io/docs/titan/overview
> diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile
> index 454d849a6ce4c..dfd15c064d078 100644
> --- a/arch/riscv/boot/dts/ultrarisc/Makefile
> +++ b/arch/riscv/boot/dts/ultrarisc/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb
> dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb
> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..7a812e40a2496
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> + */
> +
> +#include "dp1000.dtsi"
[Severity: Medium]
Does building dp1000-milkv-titan.dtb fail when CONFIG_ARCH_ULTRARISC is
enabled?
arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan.dts includes
arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi, which
includes arch/riscv/boot/dts/ultrarisc/dp1000.dtsi (introduced in commit
65da27c69d17). In arch/riscv/boot/dts/ultrarisc/dp1000.dtsi, the plic node
is declared with a duplicated unit-address suffix:
plic: interrupt-controller@9000000@9000000 {
compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic";
reg = <0x0 0x9000000 0x0 0x4000000>;
When dtc compiles dp1000-milkv-titan.dtb, check_node_name_format() in
scripts/dtc/checks.c inspects the unit name via get_unitname(node), sees
the second '@' character, and aborts the build with a node_name_format
error:
static void check_node_name_format(struct check *c, struct dt_info *dti,
struct node *node)
{
if (strchr(get_unitname(node), '@'))
FAIL(c, dti, node, "multiple '@' characters in node name");
}
Should the plic node in arch/riscv/boot/dts/ultrarisc/dp1000.dtsi be named
interrupt-controller@9000000 instead?
[ ... ]
> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
> index 43f713bcea257..b6027420175c2 100644
> --- a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
> @@ -106,7 +106,7 @@ mdio {
> #address-cells = <1>;
> #size-cells = <0>;
>
> - phy0: phy@0 {
> + phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
[Severity: Low]
Was this change to phy0 in arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
intended to be squashed into the preceding commit 5c5bd7084b50 ("riscv: dts:
ultrarisc: Add Shenzhen Rongda M0 board device tree") rather than included
in the Milk-V Titan patch?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261024-ultrarisc-dts-v6-0-c62994d8a114@ultrarisc.com?part=7
prev parent reply other threads:[~2026-10-24 9:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-24 9:27 [PATCH v6 0/7] riscv: Add device tree support for UltraRISC DP1000 Xincheng Ji via B4 Relay
2026-10-24 9:27 ` [PATCH v6 1/7] dt-bindings: vendor-prefixes: Add shenrongda Xincheng Ji via B4 Relay
2026-10-24 9:27 ` [PATCH v6 2/7] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Xincheng Ji via B4 Relay
2026-10-24 9:27 ` [PATCH v6 3/7] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Xincheng Ji via B4 Relay
2026-10-24 9:27 ` [PATCH v6 4/7] dt-bindings: timer: Add UltraRISC DP1000 CLINT Xincheng Ji via B4 Relay
2026-10-24 9:27 ` [PATCH v6 5/7] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Xincheng Ji via B4 Relay
2026-10-24 9:43 ` sashiko-bot
2026-10-24 10:18 ` Xincheng Ji
2026-10-24 9:27 ` [PATCH v6 6/7] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Xincheng Ji via B4 Relay
2026-10-24 9:41 ` sashiko-bot
2026-10-24 9:27 ` [PATCH v6 7/7] riscv: dts: ultrarisc: Add Milk-V Titan " Xincheng Ji via B4 Relay
2026-10-24 9:50 ` sashiko-bot [this message]
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