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From: sashiko-bot@kernel.org
To: "Gregory CLEMENT" <gregory.clement@bootlin.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: interrupt-controller: add Mobileye EyeQ5 PCIe MSI controller
Date: Wed, 28 Oct 2026 16:17:54 +0000	[thread overview]
Message-ID: <sashiko-outbox-188151@kernel.org> (raw)
In-Reply-To: <20261028-eyeq5_msi-v1-1-c464752fb55f@bootlin.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: interrupt-controller: invalid gic node in eyeq5-msi example
--

commit 07c2faf713f271c288290325080b191a291097be
Author: Gregory CLEMENT <gregory.clement@bootlin.com>

dt-bindings: interrupt-controller: add Mobileye EyeQ5 PCIe MSI controller

This commit adds the Device Tree binding schema for the Mobileye EyeQ5 PCIe
MSI controller.

> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mobileye,eyeq5-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/mobileye,eyeq5-msi.yaml
> new file mode 100644
> index 0000000000000..919af55fc8a60
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mobileye,eyeq5-msi.yaml
> @@ -0,0 +1,120 @@

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/mips-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    / {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        gic: interrupt-controller {
> +            compatible = "mti,cpu-interrupt-controller";
> +            interrupt-controller;
> +            #interrupt-cells = <3>;
> +        };

[Severity: Low]
Does this gic node in examples cause dt_binding_check to fail against
Documentation/devicetree/bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml?

In mti,cpu-interrupt-controller.yaml, nodes matching mti,cpu-interrupt-controller
are required to have #address-cells set to 0 and #interrupt-cells set to 1:

  properties:
    compatible:
      const: mti,cpu-interrupt-controller

    '#interrupt-cells':
      const: 1

    '#address-cells':
      const: 0

    interrupt-controller: true

  additionalProperties: false

  required:
    - compatible
    - '#interrupt-cells'
    - '#address-cells'
    - interrupt-controller

Since msi0 uses a 3-cell MIPS GIC interrupt specifier
(<GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>), should the dummy gic provider node and
root wrapper be dropped from the example, or updated to match mti,gic.yaml?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261028-eyeq5_msi-v1-0-c464752fb55f@bootlin.com?part=1

  reply	other threads:[~2026-10-28 16:17 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-28 15:58 [PATCH 0/4] irqchip: add EyeQ5 PCIe MSI controller Gregory CLEMENT
2026-10-28 15:58 ` [PATCH 1/4] dt-bindings: interrupt-controller: add Mobileye " Gregory CLEMENT
2026-10-28 16:17   ` sashiko-bot [this message]
2026-10-29  7:35   ` Krzysztof Kozlowski
2026-10-28 15:58 ` [PATCH 2/4] irqchip: irq-eyeq5-msi: add EyeQ5 PCIe MSI controller driver Gregory CLEMENT
2026-10-28 16:22   ` sashiko-bot
2026-10-28 20:05   ` Thomas Gleixner
2026-10-28 15:58 ` [PATCH 3/4] MIPS: dts: eyeq5: add MSI controllers Gregory CLEMENT
2026-10-29  7:36   ` Krzysztof Kozlowski
2026-10-28 15:58 ` [PATCH 4/4] MAINTAINERS: add EyeQ5 MSI controller entry Gregory CLEMENT

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