Re: [PATCH v6 1/3] dt-bindings: mfd: rk8xx: add board level power hold GPIOs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: mfd: rk8xx: board power-hold GPIOs modeled as PMIC properties
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commit 675c9ae7bda27dce85ec9548a8ac2ba6bdf5bf40
Author: Yaozhong Li <yaozhonguwl@gmail.com>

dt-bindings: mfd: rk8xx: add board level power hold GPIOs

This commit adds a shared schema rockchip,rk8xx-power-hold.yaml defining
power-hold-gpios and power-hold-delay-ms properties for board-level power
hold lines, and references it across all seven Rockchip RK8xx PMIC MFD
bindings.

> diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk8xx-power-hold.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk8xx-power-hold.yaml
> new file mode 100644
> index 0000000000000..6be3e1e119f0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk8xx-power-hold.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/rockchip,rk8xx-power-hold.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip RK8xx PMIC board level power hold GPIOs
> +
> +maintainers:
> +  - Yaozhong Li <yaozhonguwl@gmail.com>
> +
> +description:
> +  Properties shared by the RK8xx PMIC bindings for boards that route power
> +  hold lines from the SoC into the board's power circuitry, which have to
> +  be released before the PMIC is asked to power the system off.
> +
> +properties:
> +  power-hold-gpios:
> +    minItems: 1
> +    maxItems: 2
> +    description: >
> +      Board level power hold lines driven by the SoC. They have to be held
> +      asserted while the system is running and released before the PMIC
> +      shutdown request is written, otherwise the rails can drop and come
> +      back up instead of staying off. Only meaningful when this PMIC is the
> +      system power controller, as the lines are released as part of its
> +      power-off path.
> +
> +      The lines are released in the order listed, and power-hold-delay-ms
> +      elapses once, after the last of them.
> +
> +  power-hold-delay-ms:
> +    default: 0
> +    description:
> +      Time to wait after releasing power-hold-gpios before the shutdown
> +      request is written, to let the lines settle.

[Severity: Medium]
As reported by Sashiko on v5 [1], should board-level SoC power circuitry
GPIOs and OS shutdown sequencing delays be modeled as properties on the
RK8xx PMIC nodes across rockchip,rk801.yaml, rockchip,rk805.yaml,
rockchip,rk806.yaml, rockchip,rk808.yaml, rockchip,rk816.yaml,
rockchip,rk817.yaml, and rockchip,rk818.yaml?

None of the Rockchip RK8xx PMIC variants have SoC-driven power-hold input
pins; as noted in the description, these lines are routed from the SoC into
board circuitry outside the PMIC.

Adding power-hold-gpios (bounded at maxItems: 2 after Firefly's vendor
kernel pmic,hold-gpio and pmic,stby-gpio properties, which on boards like
rk3399-firefly.dts and rk3399-roc-pc.dtsi correspond to the pwm-backlight
enable GPIO or the vcc_sys fixed regulator enable GPIO) and
power-hold-delay-ms to all seven PMIC bindings encodes driver-specific OS
shutdown sequencing on the PMIC node rather than describing the board's
actual power switches or regulators in Devicetree.

[1] https://lore.kernel.org/r/20261027084511.1992-2-yaozhonguwl@gmail.com

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261101154053.3874-1-yaozhonguwl@gmail.com?part=1