Re: [PATCH v13 8/8] arm64: dts: qcom: Add SM7250 devicetree file

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] arm64: dts: qcom: sm7250: child nodes under soc@0 not sorted by unit address
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commit 48e074939e46ccf1a214eda37c1751a4c6df68db
Author: Sreeshankar K <sreeshankar0910@gmail.com>

arm64: dts: qcom: Add SM7250 devicetree file

This commit adds the base devicetree file for the Qualcomm SM7250 SoC,
including CPU, PSCI, clock, interrupt, and serial console nodes.

> diff --git a/arch/arm64/boot/dts/qcom/sm7250.dtsi b/arch/arm64/boot/dts/qcom/sm7250.dtsi
> new file mode 100644
> index 0000000000000..f2e77198065a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm7250.dtsi
> @@ -0,0 +1,803 @@

[ ... ]

> +	soc: soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges = <0 0 0 0 0x10 0>;
> +		dma-ranges = <0 0 0 0 0x10 0>;

[ ... ]

> +		tcsr_mutex: hwlock@1f40000 {
> +			compatible = "qcom,tcsr-mutex";
> +			reg = <0x0 0x01f40000 0x0 0x40000>;
> +			#hwlock-cells = <1>;
> +		};
> +
> +		intc: interrupt-controller@17a00000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
> +			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		timer@17c20000 {

[ ... ]

> +		};
> +
> +		pdc: interrupt-controller@b220000 {
> +			compatible = "qcom,sm7250-pdc", "qcom,pdc";
> +			reg = <0 0xb220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> +			qcom,pdc-ranges = <0 480 42>,
> +					  <42 612 28>,
> +					  <70 63 1>,
> +					  <71 640 15>,
> +					  <86 522 52>;
> +			#interrupt-cells = <2>;
> +			interrupt-parent = <&intc>;
> +			interrupt-controller;
> +		};
> +
> +		spmi_bus: spmi@c440000 {

[Severity: Low]
As reported by Sashiko on v12 [1], under soc: soc@0 in
arch/arm64/boot/dts/qcom/sm7250.dtsi, interrupt-controller@17a00000
(0x17a00000) and timer@17c20000 (0x17c20000) are placed before
interrupt-controller@b220000 (0x0b220000) and spmi@c440000 (0x0c440000).

Should interrupt-controller@b220000 and spmi@c440000 be moved before
interrupt-controller@17a00000 so that child nodes under soc@0 are ordered by
unit address in ascending numerical order?

[1] https://lore.kernel.org/r/20261104-master-v12-6-57fbe9eef978@gmail.com

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104-master-v13-0-355b65c6f764@gmail.com?part=8