Re: [PATCH 9/9] arm64: tegra: Add CCPLEX cluster node for Tegra264

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: tegra: ccplex@30000000 translates to PCIe window 0x30000000 instead of 0x8130000000
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commit 26a0214ddb9808bcd10d28a93f2871f0b1488885
Author: Sumit Gupta <sumitg@nvidia.com>

arm64: tegra: Add CCPLEX cluster node for Tegra264

This commit adds the CCPLEX cluster node under bus@8100000000 in
tegra264.dtsi and attaches performance-domains properties to the CPU nodes
for CPU frequency scaling.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 5ab34cd09a3d0..10ea51802e8c8 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3964,6 +3964,13 @@ i2c12: i2c@c6d0000 {
>  			status = "disabled";
>  		};
>  
> +		ccplex: ccplex@30000000 {
> +			compatible = "nvidia,tegra264-ccplex-cluster";
> +			reg = <0x00 0x30000000 0x0 0x00cf0000>;
> +			#performance-domain-cells = <1>;
> +			nvidia,bpmp = <&bpmp>;
> +		};

[Severity: High]
Does ccplex@30000000 translate to CPU physical address 0x00_30000000 instead
of 0x81_30000000 here?

In arch/arm64/boot/dts/nvidia/tegra264.dtsi, the parent bus@8100000000 node
defines its ranges property as:

	bus@8100000000 {
		...
		ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */
			 <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */
			 <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */
			 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */

Because child address 0x00 0x30000000 falls within the second entry
(0x00 0x20000000..0x00 0x3fffffff), OF address translation maps it to parent
CPU address 0x00 0x30000000..0x00 0x30ceffff rather than 0x81 0x30000000.

When tegra194_cpufreq_probe() calls devm_platform_get_and_ioremap_resource()
on this node, tegra264_get_cpu_ndiv() and tegra264_set_cpu_ndiv() will read
and write the 32-bit PCIe non-prefetchable memory window at 0x00 0x30000000,
which also collides with the non-prefetchable memory aperture of pci@8420000:

		pci@8420000 {
			...
			ranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */
				 <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */
				 <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */

Since pci@c000000 under bus@8100000000 only uses 0x00 0x20000000..0x00 0x27ffffff
for its 32-bit non-prefetchable memory window, should the ranges property on
bus@8100000000 be updated so that 0x00 0x30000000 translates to
0x81 0x30000000?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261104181521.3003578-1-sumitg@nvidia.com?part=9