From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793962476; b=ju0iuiNFtR7ohPvVJTJ/arIszUVU2CD+Y0cgfkDdVBVrHj4cHVgvhtP5r2txTHGoQ4ph kYvTUAUsWO7aAAMK+uAxlJRpHITL3KC5RoEla3lstQ4HGwlOUprHa4KnyHt6c3UO/2PZz RjDcGd69y4a0Zj6hiSsVwTT5YDlKBc178w7B6gGz/YpCAjLhYy6cupItJ8nxGgHA21Ujw mTC627tPlB0q1a0oa010Em7vLnp8azLWfpAnpjaZeYu/kZmUrY647C46bSeLee8rcJHj7 ul1/ytNoNn1jlZCRc24hsdfd/yFPxzKgG1TXUn8MrgYacRmW4BQ91R3PGPG+MzjxdkA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793962476; h=Received:DKIM-Signature:Message-ID:From:Subject:Reply-To:To:Cc: In-Reply-To:References:Content-Type:Content-Transfer-Encoding:Date; bh=kt2KfflUu9wnbC5ZymY+sDmDdUTHvXazydKZivviUMo=; b=12+BT/QshdlxrOlfVblY2Wz8V02TF9XBxTgcolzUPWi8LT/ArVMUCN4eYQps5zb9Ocua v2Sa7u4D/iSXilXf/NQYbH9pqOOsCvIof7KSwyCW7CdHun16peKJphu/cM23uFYARtcp2 ivXoFfSwTcNEvVB2xwO/JFhUzi9Q69CUcIcRSxfHXFX2FMhh/TnyQahY/oo6t9WhWBnRL YIeeEb/6cJEMJjMwz24ehIO7kD5uKafwoFeeSB0im/hn5OZDcexxCzGFTj3LQrCm+PlCJ J54C2dPmzO5OvTQCzwBjlNf484lmd+r5ukTpONwW5aYMVjOHZSE6kiJM99KbblyroJA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=nYmnnTbS; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F37D606A33E for ; Fri, 6 Nov 2026 10:54:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=nYmnnTbS Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF3B41F008BC; Fri, 6 Nov 2026 10:54:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793962476; bh=kt2KfflUu9wnbC5ZymY+sDmDdUTHvXazydKZivviUMo=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=nYmnnTbSCpbpDQoPABcq/UjShHDTiAIr+ewgMop+rnrvl/G2CWCu61lP+4Uq8STTl SetSlU/dwRvx5wXyLxx0aQiCJHwKuvVx0BJX3heU9Ts+m76AwU/C41Vgx9CasjOlfx LMe7xVSfl8I6nWDSJfTNtJc9Kn2K/8dNaH7qVHIsQ1xtw6TyhQF69R6z0BwUYcu4tk dM1WKdc9xRcz8qDT3nrZiOhNdrwufPgiy3oUaEky4qcv8P1CPesUWtsnFLqef33jZg ScfqCoQv9enVrSGa/NHbVBuWBDF/yeg0fzARPq/EtHTxd7ZguxReXZTPGLjeokqotc Dad+MIlAeOv5A== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH 1/3] dt-bindings: gpu: Add CIX Sky1 Mali support Reply-To: sashiko-reviews@lists.linux.dev To: "Cunyuan Liu" Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, ojeda@kernel.org, gary@garyguo.net In-Reply-To: <20261106104735.1651267-2-cunyuan.liu@cixtech.com> References: <20261106104735.1651267-1-cunyuan.liu@cixtech.com> <20261106104735.1651267-2-cunyuan.liu@cixtech.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 06 Nov 2026 10:54:35 +0000 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Low] dt-bindings: gpu: arm,mali-valhall-csf: unwieldy per-compatible conditionals -- commit f3e7a046ab621a6ec3308f5290d9455780be0bec Author: Cunyuan Liu dt-bindings: gpu: Add CIX Sky1 Mali support This commit adds the CIX Sky1 Mali compatible string, resource constraints, and a Device Tree example to the Arm Mali Valhall CSF GPU binding schema. > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.y= aml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > index 8eccd4338a2b2..a93acc6d91ec8 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > @@ -18,6 +18,7 @@ properties: > oneOf: > - items: > - enum: > + - cix,sky1-mali > - mediatek,mt8196-mali > - nxp,imx95-mali # G310 > - rockchip,rk3588-mali > @@ -51,6 +52,9 @@ properties: > - stacks > - const: stacks > =20 > + resets: > + maxItems: 1 > + > nvmem-cells: > items: > - description: bitmask of functional shader cores > @@ -146,6 +150,34 @@ allOf: > - nvmem-cells > - nvmem-cell-names > - power-domains > + - if: > + properties: > + compatible: > + contains: > + const: cix,sky1-mali > + then: > + properties: > + clocks: > + minItems: 2 > + maxItems: 2 > + clock-names: > + items: > + - const: core > + - const: stacks > + power-domains: > + maxItems: 1 > + power-domain-names: false > + mali-supply: false > + sram-supply: false > + nvmem-cells: false > + nvmem-cell-names: false > + required: > + - clock-names > + - resets > + - power-domains > + else: > + properties: > + resets: false [Severity: Low] With each variant adding another per-compatible if-then-else block to disable properties used only by other SoCs (and setting resets: false for all other variants), the conditionals in arm,mali-valhall-csf.yaml are becoming unwieldy. Should this binding be split into separate schema documents rather than piling on more variant-specific conditionals here? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261106104735.1651= 267-1-cunyuan.liu@cixtech.com?part=3D1