Re: [PATCH v6 v6 4/9] ASoC: qcom: lpass-va-macro: Add shikra compatible

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] ASoC: qcom: lpass-va-macro: missing input mux defaults in
  va_4_1_defaults
--

commit f5d496a0928cc1f25e90cbab9d135b94a6556cb6
Author: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>

ASoC: qcom: lpass-va-macro: Add shikra compatible

This commit adds compatible support and register configuration for the
Qualcomm Shikra LPASS VA macro (LPASS codec v4.1), including adaptive
filter (ADPT) blocks and a dedicated regmap default table.

> diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c
> index 03d6434a4a126..db395674312c8 100644
> --- a/sound/soc/codecs/lpass-va-macro.c
> +++ b/sound/soc/codecs/lpass-va-macro.c

[ ... ]

> @@ -357,6 +407,119 @@ static const struct reg_default va_defaults[] = {
>  	{ CDC_VA_TX3_TX_PATH_SEC6, 0x00},
>  };
>  
> +static const struct reg_default va_4_1_defaults[] = {
> +	/* VA macro */
> +	{ CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
> +	{ CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
> +	{ CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
> +	{ CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
> +	{ CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
> +	{ CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
> +	{ CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
> +	{ CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
> +	{ CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
> +	{ CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
> +	{ CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
> +	{ CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
> +	{ CDC_VA_TOP_CSR_I2S_CLK, 0x00},
> +	{ CDC_VA_TOP_CSR_I2S_RESET, 0x00},
> +	{ CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
> +	{ CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
> +	{ CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
> +	{ CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
> +	{ CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
> +	{ CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
> +	{ CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
> +	{ CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
> +	/* VA core */
> +	{ CDC_VA_TX0_TX_PATH_CTL, 0x04},

[Severity: High]
Should va_4_1_defaults include CDC_VA_INP_MUX_ADC_MUX0_CFG0 through
CDC_VA_INP_MUX_ADC_MUX3_CFG1 like va_defaults does?

va_4_1_regmap_config uses REGCACHE_MAPLE seeded from va_4_1_defaults, and
va_macro_runtime_suspend() puts the regmap into cache-only mode.  Because
those eight mux registers back the VA DEC0..3 MUX and VA DMIC MUX0..3 DAPM
widgets, reading or updating those controls while the device is runtime
suspended misses in the maple cache and fails with -EBUSY.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261106-add_shikra_support-v6-0-2cda302237cc@oss.qualcomm.com?part=4