Re: [PATCH v2 10/15] arm64: dts: apple: t8140: Add core interrupt affinities

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: dts: apple: t8140: apple,fiq-index ordered before cpus in
  affinities
--

commit f8b309addc78ccc75edc4dfad6c0a8f6e8b87b71
Author: Myria Sarvay <myrialsarvay@gmail.com>

arm64: dts: apple: t8140: Add core interrupt affinities

This commit adds the CPU PMU interrupt affinity nodes under the AIC
interrupt controller for the Apple T8140 (A18 Pro) SoC.

> diff --git a/arch/arm64/boot/dts/apple/t8140.dtsi b/arch/arm64/boot/dts/apple/t8140.dtsi
> index 3b4f7695552b5..89a26a1b23649 100644
> --- a/arch/arm64/boot/dts/apple/t8140.dtsi
> +++ b/arch/arm64/boot/dts/apple/t8140.dtsi
> @@ -167,6 +167,19 @@ aic: interrupt-controller@301000000 {
>  			#interrupt-cells = <3>;
>  			interrupt-controller;
>  			power-domains = <&ps_aic>;
> +
> +			affinities {
> +				e-core-pmu-affinity {
> +					apple,fiq-index = <AIC_CPU_PMU_E>;
> +					cpus = <&cpu_e0 &cpu_e1
> +						&cpu_e2 &cpu_e3>;
> +				};
> +
> +				p-core-pmu-affinity {
> +					apple,fiq-index = <AIC_CPU_PMU_P>;
> +					cpus = <&cpu_p0 &cpu_p1>;
> +				};
> +			};
>  		};

[Severity: Low]
Should cpus be ordered before apple,fiq-index in e-core-pmu-affinity and
p-core-pmu-affinity?  Per the Devicetree coding style, common properties
without a vendor prefix come before vendor-specific properties, and
placing apple,fiq-index first triggers warnings from
scripts/dtc/dt-check-style --mode=strict (unlike 84a1163b0a3e ("arm64:
dts: apple: t8132: Fix ordering-related dt-check-style issues") and
commit "arm64: dts: apple: t603*: Add core interrupt affinities" earlier
in this series).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261107-m3-plus-pmu-events-v2-0-acf1e78da039@gmail.com?part=10