Devicetree
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Jiaxing Hu" <gahing@gahingwoo.com>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v16 09/16] pmdomain: rockchip: add optional per-domain power-on settle delay
Date: Sun, 08 Nov 2026 07:31:35 +0000	[thread overview]
Message-ID: <sashiko-outbox-203627@kernel.org> (raw)
In-Reply-To: <20261108065917.135194-10-gahing@gahingwoo.com>

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] pmdomain: rockchip: parent-only power-off in
  rockchip_pm_add_one_domain()
--

commit 5d8e79daba54d22313c6250b1a4b08b82d2c38cf
Author: Jiaxing Hu <gahing@gahingwoo.com>

pmdomain: rockchip: add optional per-domain power-on settle delay

This commit adds an optional per-domain delay_us field to wait after
releasing the NIU idle request and before restoring QoS registers, and
sets a 15 us delay on the RK3576 NPUTOP, NPU0, and NPU1 domains while
enabling need_regulator on the RK3576 NPU parent domain.

> diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> index db3879846db67..e3cc60fa22771 100644
> --- a/drivers/pmdomain/rockchip/pm-domains.c
> +++ b/drivers/pmdomain/rockchip/pm-domains.c
[ ... ]
> @@ -1314,25 +1325,26 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
>  };
>  
>  static const struct rockchip_domain_info rk3576_pm_domains[] = {
> -	[RK3576_PD_NPU]		= DOMAIN_RK3576("npu",    0x0, BIT(0),  BIT(0), 0,       0x0, 0,       0,       0,       false),
> -	[RK3576_PD_NVM]		= DOMAIN_RK3576("nvm",    0x0, BIT(6),  0,      BIT(6),  0x4, BIT(2),  BIT(18), BIT(2),  false),
> -	[RK3576_PD_SDGMAC]	= DOMAIN_RK3576("sdgmac", 0x0, BIT(7),  0,      BIT(7),  0x4, BIT(1),  BIT(17), 0x6,     false),
> -	[RK3576_PD_AUDIO]	= DOMAIN_RK3576("audio",  0x0, BIT(8),  0,      BIT(8),  0x4, BIT(0),  BIT(16), BIT(0),  false),
> -	[RK3576_PD_PHP]		= DOMAIN_RK3576("php",    0x0, BIT(9),  0,      BIT(9),  0x0, BIT(15), BIT(15), BIT(15), false),
> -	[RK3576_PD_SUBPHP]	= DOMAIN_RK3576("subphp", 0x0, BIT(10), 0,      BIT(10), 0x0, 0,       0,       0,       false),
> -	[RK3576_PD_VOP]		= DOMAIN_RK3576("vop",    0x0, BIT(11), 0,      BIT(11), 0x0, 0x6000,  0x6000,  0x6000,  false),
> -	[RK3576_PD_VO1]		= DOMAIN_RK3576("vo1",    0x0, BIT(14), 0,      BIT(14), 0x0, BIT(12), BIT(12), 0x7000,  false),
> -	[RK3576_PD_VO0]		= DOMAIN_RK3576("vo0",    0x0, BIT(15), 0,      BIT(15), 0x0, BIT(11), BIT(11), 0x6800,  false),
> -	[RK3576_PD_USB]		= DOMAIN_RK3576("usb",    0x4, BIT(0),  0,      BIT(16), 0x0, BIT(10), BIT(10), 0x6400,  true),
> -	[RK3576_PD_VI]		= DOMAIN_RK3576("vi",     0x4, BIT(1),  0,      BIT(17), 0x0, BIT(9),  BIT(9),  BIT(9),  false),
> -	[RK3576_PD_VEPU0]	= DOMAIN_RK3576("vepu0",  0x4, BIT(2),  0,      BIT(18), 0x0, BIT(7),  BIT(7),  0x280,   false),
> -	[RK3576_PD_VEPU1]	= DOMAIN_RK3576("vepu1",  0x4, BIT(3),  0,      BIT(19), 0x0, BIT(8),  BIT(8),  BIT(8),  false),
> -	[RK3576_PD_VDEC]	= DOMAIN_RK3576("vdec",   0x4, BIT(4),  0,      BIT(20), 0x0, BIT(6),  BIT(6),  BIT(6),  false),
> -	[RK3576_PD_VPU]		= DOMAIN_RK3576("vpu",    0x4, BIT(5),  0,      BIT(21), 0x0, BIT(5),  BIT(5),  BIT(5),  false),
> -	[RK3576_PD_NPUTOP]	= DOMAIN_RK3576("nputop", 0x4, BIT(6),  0,      BIT(22), 0x0, 0x18,    0x18,    0x18,    false),
> -	[RK3576_PD_NPU0]	= DOMAIN_RK3576("npu0",   0x4, BIT(7),  0,      BIT(23), 0x0, BIT(1),  BIT(1),  0x1a,    false),
> -	[RK3576_PD_NPU1]	= DOMAIN_RK3576("npu1",   0x4, BIT(8),  0,      BIT(24), 0x0, BIT(2),  BIT(2),  0x1c,    false),
> -	[RK3576_PD_GPU]		= DOMAIN_RK3576("gpu",    0x4, BIT(9),  0,      BIT(25), 0x0, BIT(0),  BIT(0),  BIT(0),  false),
> +	/*                                            name    p_offset pwr      status  r_status r_offset req      idle     g_mask   delay wakeup */
> +	[RK3576_PD_NPU]		= DOMAIN_RK3576_R("npu",  0x0, BIT(0),  BIT(0), 0,       0x0, 0,       0,       0,       0,    false),
> +	[RK3576_PD_NVM]		= DOMAIN_RK3576("nvm",    0x0, BIT(6),  0,      BIT(6),  0x4, BIT(2),  BIT(18), BIT(2),  0,    false),
> +	[RK3576_PD_SDGMAC]	= DOMAIN_RK3576("sdgmac", 0x0, BIT(7),  0,      BIT(7),  0x4, BIT(1),  BIT(17), 0x6,     0,    false),
> +	[RK3576_PD_AUDIO]	= DOMAIN_RK3576("audio",  0x0, BIT(8),  0,      BIT(8),  0x4, BIT(0),  BIT(16), BIT(0),  0,    false),
> +	[RK3576_PD_PHP]		= DOMAIN_RK3576("php",    0x0, BIT(9),  0,      BIT(9),  0x0, BIT(15), BIT(15), BIT(15), 0,    false),
> +	[RK3576_PD_SUBPHP]	= DOMAIN_RK3576("subphp", 0x0, BIT(10), 0,      BIT(10), 0x0, 0,       0,       0,       0,    false),
> +	[RK3576_PD_VOP]		= DOMAIN_RK3576("vop",    0x0, BIT(11), 0,      BIT(11), 0x0, 0x6000,  0x6000,  0x6000,  0,    false),
> +	[RK3576_PD_VO1]		= DOMAIN_RK3576("vo1",    0x0, BIT(14), 0,      BIT(14), 0x0, BIT(12), BIT(12), 0x7000,  0,    false),
> +	[RK3576_PD_VO0]		= DOMAIN_RK3576("vo0",    0x0, BIT(15), 0,      BIT(15), 0x0, BIT(11), BIT(11), 0x6800,  0,    false),
> +	[RK3576_PD_USB]		= DOMAIN_RK3576("usb",    0x4, BIT(0),  0,      BIT(16), 0x0, BIT(10), BIT(10), 0x6400,  0,    true),
> +	[RK3576_PD_VI]		= DOMAIN_RK3576("vi",     0x4, BIT(1),  0,      BIT(17), 0x0, BIT(9),  BIT(9),  BIT(9),  0,    false),
> +	[RK3576_PD_VEPU0]	= DOMAIN_RK3576("vepu0",  0x4, BIT(2),  0,      BIT(18), 0x0, BIT(7),  BIT(7),  0x280,   0,    false),
> +	[RK3576_PD_VEPU1]	= DOMAIN_RK3576("vepu1",  0x4, BIT(3),  0,      BIT(19), 0x0, BIT(8),  BIT(8),  BIT(8),  0,    false),
> +	[RK3576_PD_VDEC]	= DOMAIN_RK3576("vdec",   0x4, BIT(4),  0,      BIT(20), 0x0, BIT(6),  BIT(6),  BIT(6),  0,    false),
> +	[RK3576_PD_VPU]		= DOMAIN_RK3576("vpu",    0x4, BIT(5),  0,      BIT(21), 0x0, BIT(5),  BIT(5),  BIT(5),  0,    false),
> +	[RK3576_PD_NPUTOP]	= DOMAIN_RK3576("nputop", 0x4, BIT(6),  0,      BIT(22), 0x0, 0x18,    0x18,    0x18,    15,   false),
> +	[RK3576_PD_NPU0]	= DOMAIN_RK3576("npu0",   0x4, BIT(7),  0,      BIT(23), 0x0, BIT(1),  BIT(1),  0x1a,    15,   false),
> +	[RK3576_PD_NPU1]	= DOMAIN_RK3576("npu1",   0x4, BIT(8),  0,      BIT(24), 0x0, BIT(2),  BIT(2),  0x1c,    15,   false),

[Severity: High]
When the bootloader leaves the NPU powered on, does setting
need_regulator only on the parent RK3576_PD_NPU domain cause
rockchip_pm_domain_probe() to either fail in pm_genpd_add_subdomain() or
leave the child NPU domains in an inconsistent power state?

During probe, rockchip_pm_add_one_domain() runs top-down on
RK3576_PD_NPU before rockchip_pm_add_subdomain() visits its child
RK3576_PD_NPUTOP and grandchildren RK3576_PD_NPU0 and RK3576_PD_NPU1:

drivers/pmdomain/rockchip/pm-domains.c:rockchip_pm_add_one_domain() {
	...
	if (pd->info->need_regulator)
		rockchip_pd_power(pd, false);
	...
	pm_genpd_init(&pd->genpd, NULL,
		      !rockchip_pmu_domain_is_on(pd) ||
		      (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
}

Because RK3576_PD_NPUTOP, RK3576_PD_NPU0, and RK3576_PD_NPU1 still use
DOMAIN_RK3576 (need_regulator = false), rockchip_pm_add_one_domain()
never powers them off.  If RK3576_PD_NPU powers off while
RK3576_PD_NPUTOP still reports on via its repair_status_mask and
mem_status_mask bits, RK3576_PD_NPU initializes as GENPD_STATE_OFF and
RK3576_PD_NPUTOP initializes as GENPD_STATE_ON, causing
pm_genpd_add_subdomain() to return -EINVAL and abort probe for all
domains on the SoC.  Conversely, if hardware refuses to power off
RK3576_PD_NPU while its children are on (with the rockchip_pd_power()
error ignored), all NPU domains stay in GENPD_STATE_ON without enabling
the supply regulator or running the 15 us delay; or if cutting parent
power forces child status bits low in hardware, it cuts power while child
NIU buses are un-idled and leaves child pwr_offset 0x4 control bits set,
so once RK3576_PD_NPU powers back on, rockchip_pd_power(pd, true) on the
children sees rockchip_pmu_domain_is_on(pd) == true and returns early
without running udelay() or rockchip_pmu_restore_qos().

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108065917.135194-1-gahing@gahingwoo.com?part=9

  reply	other threads:[~2026-11-08  7:31 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-08  6:59 [PATCH v16 00/16] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 01/16] accel/rocket: request the core clocks by name Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 02/16] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 03/16] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-11-08  7:25   ` sashiko-bot
2026-11-08  6:59 ` [PATCH v16 04/16] accel/rocket: let the core suspend after a reset Jiaxing Hu
2026-11-08  7:26   ` sashiko-bot
2026-11-08  6:59 ` [PATCH v16 05/16] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 06/16] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-11-08  7:08   ` [PATCH v16 06/16] dt-bindings: npu: rockchip: add rockchip, rk3576-rknn-core sashiko-bot
2026-11-08  6:59 ` [PATCH v16 07/16] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 08/16] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 09/16] pmdomain: rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-11-08  7:31   ` sashiko-bot [this message]
2026-11-11  7:46   ` Finley Xiao
2026-11-08  6:59 ` [PATCH v16 10/16] pmdomain: rockchip: cycle an optional power-domain reset on power-on Jiaxing Hu
2026-11-11  8:23   ` Finley Xiao
2026-11-08  6:59 ` [PATCH v16 11/16] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 12/16] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 13/16] accel/rocket: add a GET_PARAM ioctl for the hardware version Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 14/16] arm64: dts: rockchip: add NPU core domain clocks and resets to rk3576 Jiaxing Hu
2026-11-11  9:06   ` Finley Xiao
2026-11-08  6:59 ` [PATCH v16 15/16] arm64: dts: rockchip: add NPU (RKNN) nodes " Jiaxing Hu
2026-11-08  6:59 ` [PATCH v16 16/16] arm64: dts: rockchip: enable the NPU on rk3576-rock-4d Jiaxing Hu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=sashiko-outbox-203627@kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=gahing@gahingwoo.com \
    --cc=robh@kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox