Re: [PATCH v5 7/7] arm64: dts: qcom: nord: Add MPAM MSC nodes for the L2 caches

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: dts: qcom: nord: undocumented qcom,nord-l2-cache
  compatible string
--

commit 945c2648afac411c203b55a624505e915359df08
Author: Yin Li <yin.li@oss.qualcomm.com>

arm64: dts: qcom: nord: Add MPAM MSC nodes for the L2 caches

This commit moves the L2 cache nodes out of the CPU nodes to the root node
and adds child MPAM MSC device nodes under each L2 cache.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index fdbe290350ddd..285c6a3e5cb7d 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi

[ ... ]

> @@ -907,6 +889,60 @@ dump_mem: mem-dump-region {
>  		};
>  	};
>  
> +	l2_0: cache@19870000 {
> +		compatible = "qcom,nord-l2-cache", "cache";
> +		cache-level = <2>;
> +		cache-unified;
> +		cache-size = <0xc00000>;
> +		reg = <0x0 0x19870000 0x0 0x2000>;
> +		ranges = <0x0 0x0 0x19870000 0x2000>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		msc@0 {
> +			compatible = "arm,mpam-msc";
> +			reg = <0x0 0x2000>;
> +			arm,not-ready-us = <1>;
> +		};
> +	};
> +
> +	l2_10000: cache@1a870000 {
> +		compatible = "qcom,nord-l2-cache", "cache";
> +		cache-level = <2>;
> +		cache-unified;
> +		cache-size = <0xc00000>;
> +		reg = <0x0 0x1a870000 0x0 0x2000>;
> +		ranges = <0x0 0x0 0x1a870000 0x2000>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		msc@0 {
> +			compatible = "arm,mpam-msc";
> +			reg = <0x0 0x2000>;
> +			arm,not-ready-us = <1>;
> +		};
> +	};
> +
> +	l2_20000: cache@1b870000 {
> +		compatible = "qcom,nord-l2-cache", "cache";
> +		cache-level = <2>;
> +		cache-unified;
> +		cache-size = <0xc00000>;
> +		reg = <0x0 0x1b870000 0x0 0x2000>;
> +		ranges = <0x0 0x0 0x1b870000 0x2000>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		msc@0 {
> +			compatible = "arm,mpam-msc";
> +			reg = <0x0 0x2000>;
> +			arm,not-ready-us = <1>;
> +		};
> +	};

[Severity: Low]
Is a Devicetree binding schema missing for "qcom,nord-l2-cache"?

"qcom,nord-l2-cache" is not documented under
Documentation/devicetree/bindings/, and the generic schemas/cache.yaml in
dtschema only matches const "cache" with additionalProperties: false, which
rejects reg, ranges, #address-cells, #size-cells, and the child msc@0 node.
As a result, both checkpatch.pl and make dtbs_check fail validation on the
l2_0, l2_10000, and l2_20000 nodes.

Also, per Documentation/devicetree/bindings/dts-coding-style.rst, reg and
ranges should be placed immediately after compatible, before cache-level,
cache-unified, and cache-size.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-mpam-resctrl-dt-knp-support-v5-0-150335a79381@oss.qualcomm.com?part=7