Re: [PATCH v2 2/2] arm64: dts: qcom: sm8350: Add the inline crypto engine

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: dts: qcom: sm8350: ICE reg size 0x11000 instead of
  0x18000
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commit b6d71a017150b9b7aef8d2a54ca324fd569ec504
Author: Demeter Barna <me@fromdisposition.org>

arm64: dts: qcom: sm8350: Add the inline crypto engine

This commit adds the UFS inline crypto engine (ICE) device node to the
SM8350 device tree and links it from the UFS host controller node via
qcom,ice.

> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 55b32050ce9c8..2b258c4b4fa71 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi

[ ... ]

> @@ -1807,6 +1809,17 @@ ufs_mem_phy: phy@1d87000 {
>  			status = "disabled";
>  		};
>  
> +		ice: crypto@1d88000 {
> +			compatible = "qcom,sm8350-inline-crypto-engine",
> +				     "qcom,inline-crypto-engine";
> +			reg = <0 0x01d88000 0 0x11000>;

[Severity: Low]
Should the ICE register region size be 0x18000 (0x8000 for ICE + 0x10000
for HWKM) instead of 0x11000?

Other Qualcomm SoCs with ICE v3.2.0+ and HWKM at 0x01d88000 define this
aperture as 0x18000, including Kodiak in fa9c7403af64 ("arm64: dts: qcom:
kodiak: Fix ICE reg size") and SM8450 in 7fb3d0512dac ("arm64: dts: qcom:
sm8450: Fix ICE reg size").  While drivers/soc/qcom/ice.c currently
accesses up to offset 0xd010 (QCOM_ICE_REG_HWKM_BANK0_BBAC_4), mapping
only 0x11000 leaves the upper 0x7000 bytes of the HWKM register space
unmapped.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-b4-sm8350-ice-v2-0-fd5e84985e90@fromdisposition.org?part=2