Re: [PATCH 1/8] dt-bindings: media: Add qcom,sm8150-camss

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] dt-bindings: media: qcom,sm8150-camss: wrong CSIPHY regulator
  supply voltages
- [Low] dt-bindings: media: qcom,sm8150-camss: drop non-programmable
  clock-lanes
--

commit 0fb4333890ec99f90c8e1d28d189ea7add0c4129
Author: Gaurav Suman <gauravsuman007@gmail.com>

dt-bindings: media: Add qcom,sm8150-camss

This commit adds the Device Tree binding schema for the Qualcomm SM8150
Camera Subsystem (CAMSS).

> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
> new file mode 100644
> index 0000000000000..e13bcd8d48adf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8150-camss.yaml
> @@ -0,0 +1,389 @@

[ ... ]

> +  vdd-csiphy-1p2-supply:
> +    description:
> +      Phandle to a 1.2V regulator supply to CSI PHYs.
> +
> +  vdd-csiphy-1p8-supply:
> +    description:
> +      Phandle to a 1.8V regulator supply to CSI PHYs pll block.

[Severity: Medium]
Are these the right CSIPHY supply voltages for SM8150?

On SM8150 boards (such as sm8150-hdk.dts and sm8150-mtp.dts), the four CSI
PHY core rails (vdda_csi_0_0p9 through vdda_csi_3_0p9) are supplied by the
0.88V PM8150 LDO5 regulator (vreg_l5a_0p875), and the PLL supply on 3PH
CSIPHY hardware is 1.2V rather than 1.8V.  Requiring 1.2V and 1.8V supplies
here (and wiring them to vreg_l3c_1p2 and vreg_l1c_1p8 in the example) leaves
the 0.88V CSIPHY core rail undescribed and unpowered.

> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    description:
> +      CSI input ports.
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/$defs/port-base
> +        unevaluatedProperties: false
> +        description:
> +          Input port for receiving CSI data from CSIPHY0.
> +
> +        properties:
> +          endpoint:
> +            $ref: video-interfaces.yaml#
> +            unevaluatedProperties: false
> +
> +            properties:
> +              clock-lanes:
> +                maxItems: 1
> +
> +              data-lanes:
> +                minItems: 1
> +                maxItems: 4

[Severity: Low]
Should clock-lanes be dropped from port@0 through port@3 and from the
example below?

On Qualcomm 3PH CSIPHY hardware the clock lane position is fixed in
hardware and not programmable by the CAMSS driver, which is why commit
336136e197e2 ("media: dt-bindings: media: camss: Remove clock-lane
property") and commit b8ef764aff5be ("dt-bindings: media:
qcom,x1e80100-camss: Remove clock-lanes port property") removed it from the
other CAMSS bindings.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-sm8150-camera-v1-0-3d2e7b407516@gmail.com?part=1