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From: sashiko-bot@kernel.org
To: "Arun Iyengar" <aiyengar1990@gmail.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks
Date: Tue, 10 Nov 2026 07:23:47 +0000	[thread overview]
Message-ID: <sashiko-outbox-206483@kernel.org> (raw)
In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-2-628819ca44b9@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: iommu: arm,smmu-v3: unconstrained clocks property
--

commit 42a979d69e35794390e397c67d04e277f3c21933
Author: Arun Iyengar <aiyengar1990@gmail.com>

dt-bindings: iommu: arm,smmu-v3: allow clocks

This commit adds an optional clocks property allowing between one and four
clocks to the arm,smmu-v3 Devicetree binding schema.

> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c8f22dfdb1dbc..f8a74730667c8 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -63,6 +63,13 @@ properties:
>  
>    msi-parent: true
>  
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +    description:
> +      Clocks needed to access the SMMU registers and to keep its translation
> +      units running, if they are not managed by firmware.

[Severity: Low]
Should clocks be constrained with an explicit items list, clock-names, or
implementation-specific compatible strings instead of allowing 1 to 4
unidentified clocks on the generic arm,smmu-v3 binding?

The SMMUv3 architecture does not define clock inputs, as clocks depend on
the specific implementation (such as MMU-600) and SoC integration.
Allowing up to four clocks without per-item descriptions or clock-names
(which is rejected by additionalProperties: false) leaves the clock
ordering and identity ambiguous whenever multiple clocks are present.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110-smmu-v3-pcie-pd-v1-0-628819ca44b9@gmail.com?part=2

  reply	other threads:[~2026-11-10  7:23 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10  7:11 [PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU Arun Iyengar via B4 Relay
2026-11-10  7:11 ` [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain Arun Iyengar via B4 Relay
2026-11-10 14:51   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks Arun Iyengar via B4 Relay
2026-11-10  7:23   ` sashiko-bot [this message]
2026-11-10 14:55   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks Arun Iyengar via B4 Relay
2026-11-10  7:26   ` sashiko-bot
2026-11-10 14:53   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU Arun Iyengar via B4 Relay
2026-11-10 15:00   ` Sebastian Reichel
2026-11-11  6:53   ` Shawn Lin
2026-11-10  7:11 ` [PATCH 5/5] arm64: dts: rockchip: add the clock of " Arun Iyengar via B4 Relay
2026-11-10 15:07   ` Sebastian Reichel
2026-11-10  8:40 ` [PATCH 0/5] iommu/arm-smmu-v3: power domain and " Shawn Lin
2026-11-10  8:49   ` Heiko Stübner
2026-11-11  8:02     ` Shawn Lin
2026-11-11  9:53       ` Heiko Stübner
2026-11-12  3:50         ` Sebastian Reichel
2026-11-10 15:13 ` Sebastian Reichel

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