From: sashiko-bot@kernel.org
To: "Rosen Penev" <rosenp@gmail.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 6/7] clk: add a driver for the Atheros/Qualcomm ath79 PLL controller
Date: Wed, 11 Nov 2026 22:14:41 +0000 [thread overview]
Message-ID: <sashiko-outbox-209774@kernel.org> (raw)
In-Reply-To: <20261111215729.10683-7-rosenp@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] clk: ath79: zeroed hfrac shift in qca956x_pll_rate()
--
commit 423abf763de32c1b127032d8210181c833b02aa9
Author: Rosen Penev <rosenp@gmail.com>
clk: add a driver for the Atheros/Qualcomm ath79 PLL controller
This commit adds a common clock driver for the Atheros/Qualcomm ath79 PLL
controller to replace the arch/mips/ath79/clock.c setup code.
> diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> new file mode 100644
> index 0000000000000..6eab4cd1a91f7
> --- /dev/null
> +++ b/drivers/clk/clk-ath79.c
> @@ -0,0 +1,782 @@
[ ... ]
> +#define QCA956X_PLL_CONFIG1_NFRAC_L GENMASK(4, 0)
> +#define QCA956X_PLL_CONFIG1_NFRAC_H GENMASK(17, 5)
> +#define QCA956X_PLL_CONFIG1_NINT GENMASK(26, 18)
[ ... ]
> +static unsigned long qca956x_pll_rate(unsigned long ref, u32 config,
> + u32 config1, u32 refdiv_mask,
> + u32 outdiv_mask)
> +{
> + u32 ref_div, out_div, nint, hfrac, lfrac;
> + u64 rate;
> +
> + ref_div = (config & refdiv_mask) >> __ffs(refdiv_mask);
> + out_div = (config & outdiv_mask) >> __ffs(outdiv_mask);
> + nint = FIELD_GET(QCA956X_PLL_CONFIG1_NINT, config1);
> + hfrac = FIELD_GET(QCA956X_PLL_CONFIG1_NFRAC_H, config1);
> + lfrac = FIELD_GET(QCA956X_PLL_CONFIG1_NFRAC_L, config1);
> +
> + if (!ref_div)
> + return 0;
> +
> + rate = div_u64((u64)ref * nint, ref_div);
> + rate += div_u64((u64)ref * lfrac, (ref_div * 25) << 13);
> + rate += div_u64((u64)ref * (hfrac >> 13), ref_div);
[Severity: Medium]
Does (hfrac >> 13) always evaluate to 0 here? QCA956X_PLL_CONFIG1_NFRAC_H
is a 13-bit mask (GENMASK(17, 5)), so hfrac is at most 0x1fff and shifting
it right by 13 drops the upper fractional multiplier completely when
computing the QCA956x CPU, DDR, and AHB clock rates. Matching the lfrac
term above, it looks like the divisor should be shifted instead:
div_u64((u64)ref * hfrac, ref_div << 13).
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261111215729.10683-1-rosenp@gmail.com?part=6
next prev parent reply other threads:[~2026-11-11 22:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-11 21:57 [PATCH v3 0/7] clk: add a driver for the ath79 PLL controller Rosen Penev
2026-11-11 21:57 ` [PATCH v3 1/7] MIPS: ath79: apply the QCA956x timer workaround in setup Rosen Penev
2026-11-11 21:57 ` [PATCH v3 2/7] MIPS: ath79: move the bootstrap reference clock to setup Rosen Penev
2026-11-11 21:57 ` [PATCH v3 3/7] MIPS: ath79: stop using ATH79_CLK_END Rosen Penev
2026-11-11 21:57 ` [PATCH v3 4/7] dt-bindings: clock: ath79: drop ATH79_CLK_END Rosen Penev
2026-11-12 10:48 ` Krzysztof Kozlowski
2026-11-11 21:57 ` [PATCH v3 5/7] dt-bindings: clock: ath79: add the UART1 and PCIe PLL clocks Rosen Penev
2026-11-12 10:48 ` Krzysztof Kozlowski
2026-11-11 21:57 ` [PATCH v3 6/7] clk: add a driver for the Atheros/Qualcomm ath79 PLL controller Rosen Penev
2026-11-11 22:14 ` sashiko-bot [this message]
2026-11-11 22:29 ` Rosen Penev
2026-11-11 21:57 ` [PATCH v3 7/7] MIPS: ath79: remove the old clock code Rosen Penev
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