Re: [PATCH v4 3/3] arm64: dts: qcom: sm8750: describe all MDSS block resets

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: sm8750: wrong DISP_CC_MDSS_CORE_INT2_BCR
  reset on mdss
--

commit 40e1c76742905572ea3b661e7e1c52df77536978
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

arm64: dts: qcom: sm8750: describe all MDSS block resets

This commit adds a second display clock controller reset to the mdss node in
the sm8750 device tree.

> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index cf947acc57602..0f3e649787315 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3359,7 +3359,8 @@ mdss: display-subsystem@ae00000 {
>  				 <&gcc GCC_DISP_HF_AXI_CLK>,
>  				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
>  
> -			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>,
> +				 <&dispcc DISP_CC_MDSS_CORE_INT2_BCR>;

[Severity: Medium]
Is the second reset entry actually for an interrupt controller rather than a
separate secondary display core domain?

In drivers/clk/qcom/dispcc-sm8750.c, the 0x8000..0x9000 register block holds
the primary display core reset, primary clocks (disp_cc_mdss_mdp_clk,
disp_cc_mdss_ahb_clk) and mdss_gdsc, whereas 0xa000..0xb000 is a secondary
domain with its own clocks (disp_cc_mdss_mdp1_clk, disp_cc_mdss_ahb1_clk,
etc.) and dedicated power domain (mdss_int2_gdsc at 0xb000):

drivers/clk/qcom/dispcc-sm8750.c:
static const struct qcom_reset_map disp_cc_sm8750_resets[] = {
	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
};

static struct gdsc *disp_cc_sm8750_gdscs[] = {
	[MDSS_GDSC] = &mdss_gdsc,
	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
};

The mdss interrupt controller in drivers/gpu/drm/msm/msm_mdss.c lives at
offset 0x10 in the primary mdss register space, which is powered by
mdss_gdsc and reset by the primary core reset.  Wiring the second reset here
causes msm_mdss_reset() to assert and deassert the block reset of a separate
clock and power domain whose gdsc and clocks are not attached to the mdss
device.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1794558882.git.xiaqinghuan@mail.ustc.edu.cn?part=3