Re: [PATCH v4 2/2] arm64: dts: qcom: nord: wire up GPI DMA for QUP I2C/SPI engines

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] arm64: dts: qcom: nord: QCOM_GPI_SPI DMA properties added to
  UART nodes
- [Medium] arm64: dts: qcom: nord: missing GPI DMA properties on spi4
  and spi14..spi19
--

commit 9c6fd2386259cb23b0a0394993d22bac655549bb
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

arm64: dts: qcom: nord: wire up GPI DMA for QUP I2C/SPI engines

This commit adds GPI DMA channel phandles and dma-names properties to QUPv3
I2C and SPI serial engine nodes in nord.dtsi.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index 68787db708f61..818f6054bcec8 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi

[ ... ]

> @@ -1244,6 +1272,10 @@ spi20: spi@898000 {
>  				reg = <0x0 0x00898000 0x0 0x4000>;
>  				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
>  
> +				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
> +				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +
>  				status = "disabled";
>  			};
>  

[Severity: Medium]
Were the GPI DMA properties for spi14 through spi19 (on gpi_dma2 SE 0..5)
and spi4 (on gpi_dma0 SE 4) accidentally omitted?

All seven I2C nodes in qupv3_2 (i2c14..i2c20) and all six I2C nodes in
qupv3_0 (i2c0..i2c5) are wired up, but among the SPI nodes in qupv3_2 only
spi20 receives gpi_dma2 channels, and spi4 in qupv3_0 is also skipped.  In
particular, spi16 (spi@888000) is enabled on Nord Ride and Nord RRD, so
spi_geni_grab_gpi_chan() will fail to acquire the tx and rx DMA channels
when FIFO_IF_DISABLE is set and fall back to FIFO mode.

[ ... ]

> @@ -1309,6 +1345,10 @@ uart0: serial@980000 {
>  				reg = <0x0 0x00980000 0x0 0x4000>;
>  				interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
>  
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +
>  				status = "disabled";
>  			};
>  

[Severity: Medium]
As reported by Konrad Dybcio on v3 [1], should these QCOM_GPI_SPI DMA
channels be added to spi0..spi3, spi7..spi8, and spi11..spi12 instead of
their sibling UART nodes (uart0..uart3, uart7..uart8, and uart11..uart12)?

Those eight SPI nodes are left without GPI DMA channels, causing
spi_geni_grab_gpi_chan() to fail to acquire tx and rx DMA channels when
FIFO_IF_DISABLE is set, while the UART nodes gain dmas and dma-names
properties that are not permitted by the GENI UART bindings.

[1] https://lore.kernel.org/r/6e91b34f-367e-4835-a7ce-e899953a5bd1@oss.qualcomm.com

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261113-nord-gpi-dts-v4-0-e4a1510687c0@oss.qualcomm.com?part=2