From: sashiko-bot@kernel.org
To: "Han Gao" <gaohan@iscas.ac.cn>
Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org,
linux-gpio@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH 06/19] clk: sunxi-ng: add support for the Allwinner V861 CCU
Date: Fri, 13 Nov 2026 22:46:34 +0000 [thread overview]
Message-ID: <sashiko-outbox-213839@kernel.org> (raw)
In-Reply-To: <20261114-v861-v1-6-eb71ec3ee523@iscas.ac.cn>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] clk: sunxi-ng: ccu_mp_set_rate() ignores
CCU_FEATURE_UPDATE_BIT for dram_clk
--
commit 4dcfa888826dc579312b5e254290daa03aed3f59
Author: Han Gao <gaohan@iscas.ac.cn>
clk: sunxi-ng: add support for the Allwinner V861 CCU
This commit adds the main CCU clock and reset driver for the Allwinner
V861 SoC.
> diff --git a/drivers/clk/sunxi-ng/ccu-sun252i-v861.c b/drivers/clk/sunxi-ng/ccu-sun252i-v861.c
> new file mode 100644
> index 0000000000000..af84c49fbaf16
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun252i-v861.c
[ ... ]
> +static const struct clk_parent_data dram_parents[] = {
> + { .fw_name = "hosc" },
> + { .hw = &pll_ddr_clk.common.hw },
> + { .hw = &pll_periph0_2x_clk.common.hw },
> + { .hw = &pll_periph0_800M_clk.common.hw },
> +};
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
> + 0x800,
> + 0, 5, /* M */
> + 8, 2, /* P */
> + 24, 3, /* mux */
> + BIT(31), /* gate */
> + CLK_IS_CRITICAL,
> + CCU_FEATURE_UPDATE_BIT);
[Severity: Medium]
Does changing the rate of dram_clk actually latch the new dividers in
hardware?
dram_clk uses ccu_mp_ops with CCU_FEATURE_UPDATE_BIT, but unlike
ccu_div_set_rate(), ccu_mp_set_rate() never checks CCU_FEATURE_UPDATE_BIT
or sets CCU_SUNXI_UPDATE_BIT before writing the register:
drivers/clk/sunxi-ng/ccu_mp.c:ccu_mp_set_rate() {
...
if (shift)
reg |= ilog2(p) << cmp->p.shift;
else
reg |= (p - cmp->p.offset) << cmp->p.shift;
writel(reg, cmp->common.base + cmp->common.reg);
...
}
When clk_set_rate() updates the M or P dividers without a parent mux or
gate change, the hardware ignores the unlatched divider update while
ccu_mp_recalc_rate() reads back the new register fields and reports the
wrong rate to the clock framework and child clocks such as mbus_clk.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261114-v861-v1-0-eb71ec3ee523@iscas.ac.cn?part=6
next prev parent reply other threads:[~2026-11-13 22:46 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 22:33 [PATCH 00/19] riscv: add initial support for the Allwinner V861 and Avaota F2 Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 01/19] riscv: sunxi: describe the wider Allwinner SoC family Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 02/19] dt-bindings: riscv: cpus: add the XuanTie C907 Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 03/19] dt-bindings: interrupt-controller: add the Allwinner V861 PLIC Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 04/19] dt-bindings: timer: add the Allwinner V861 CLINT Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 05/19] dt-bindings: clock: sunxi-ng: document the Allwinner V861 CCUs Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 06/19] clk: sunxi-ng: add support for the Allwinner V861 CCU Han Gao via B4 Relay
2026-11-13 22:46 ` sashiko-bot [this message]
2026-11-13 22:33 ` [PATCH 07/19] clk: sunxi-ng: add support for the Allwinner V861 PRCM CCU Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 08/19] dt-bindings: rtc: sun6i: add the Allwinner V861 RTC Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 09/19] clk: sunxi-ng: sun6i-rtc: allow variants without a 32k fanout mux Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 10/19] clk: sunxi-ng: sun6i-rtc: allow another 24 MHz to 32k divider ratio Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 11/19] clk: sunxi-ng: sun6i-rtc: add Allwinner V861 support Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 12/19] dt-bindings: pinctrl: add the Allwinner V861 pin controllers Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 13/19] pinctrl: sunxi: allow a per-controller IRQ register base Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 14/19] pinctrl: sunxi: add support for the Allwinner V861 PIO Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 15/19] pinctrl: sunxi: add support for the Allwinner V861 R-PIO Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 16/19] riscv: dts: allwinner: add the Allwinner V861 SoC Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 17/19] dt-bindings: riscv: sunxi: add the YuzukiHD Avaota F2 Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 18/19] riscv: dts: allwinner: add the YuzukiHD Avaota F2 board Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 19/19] MAINTAINERS: add an entry for the Allwinner V861 SoC Han Gao via B4 Relay
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