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The controlle= r > > > > is similar to previous generations, but the register fields are > > > > widened, the depth is made configurable, and the enable bit moves > > > > to a different spot. > > > >=20 > > > > This series adds only basic support with fixed depth -- configurabl= e > > > > depth will come later. > > > >=20 > > > > Patch 1 adds device tree bindings for Tegra264 PWM (compatible > > > > string). > > > >=20 > > > > Patch 2 prefixes driver-local macros and static helpers with > > > > tegra_/TEGRA_ to make their scoping clear. > > > >=20 > > > > Patches 3 to 6 contain the PWM driver changes for Tegra264. > > > >=20 > > > > Patch 7 adds device tree nodes for the PWM controllers on Tegra264. > > >=20 > > > ... > > >=20 > > > > Mikko Perttunen (4): > > > > pwm: tegra: Prefix driver-local macros and functions > > > > pwm: tegra: Modify read/write accessors for multi-register c= hannel > > > > pwm: tegra: Parametrize duty and scale field widths > > > > pwm: tegra: Add support for Tegra264 > > > >=20 > > > > Thierry Reding (2): > > > > dt-bindings: pwm: Document Tegra264 controller > > > > arm64: tegra: Add PWM controllers on Tegra264 > > > >=20 > > > > Yi-Wei Wang (1): > > > > pwm: tegra: Avoid hard-coded max clock frequency > > > >=20 > > > > .../bindings/pwm/nvidia,tegra20-pwm.yaml | 1 + > > > > arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 ++++++++= ++ > > > > drivers/pwm/pwm-tegra.c | 155 > > > > +++++++++++ +++------- > > > > 3 files changed, 176 insertions(+), 52 deletions(-) > > >=20 > > >=20 > > > For the series ... > > >=20 > > > Tested-by: Jon Hunter > > > Reviewed-by: Jon Hunter > > >=20 > > > Uwe, if you are OK with the version, we would like to get this into -= next. > >=20 > > This still applies fine on next-20260629 and so unless you have any > > objections could we get this into -next? >=20 > I dropped this patch series from my queue due to sashiko's replies. I > just notice these were not sent to the linux-pwm list, otherwise I would > have mentioned it. :-( Sashiko replies are not sent to linux-tegra either, so I tend to miss them. E-mail is hard :( >=20 > So check on either >=20 > https://lore.kernel.org/all/add09636-7b0e-4a99-8503-d98a75c14f4c@nvidia.= com/ >=20 > or >=20 > https://sashiko.dev/#/patchset/20260529-t264-pwm-v5-0-7bf9e405a96a%40nvi= dia.com >=20 > . >=20 > I only invested a quick glance, but the feedback seems relevant. If you > don't agree, please point out why it's wrong/irrelevant. >=20 > Best regards > Uwe Sashiko: > Does setting the target frequency to ULONG_MAX work safely with OPP > tables? This is not a concern. The OPP tables are designed with top OPP at the maximum clock frequency. Indeed, before this patch, the hardcoded max frequency in the driver matches what ULONG_MAX gets rounded to so there is no change in functionality. Sashiko: > Is it possible for pc->clk_rate to be less than 256 here? I.e. is it possible for clk_get_rate to return 0 after we have successfully requested a rate of ULONG_MAX. I suppose that's technically possible -- maybe if the clock is virtualized and read-only and left disabled by boot? I can add a sanity check for clk_rate =3D=3D 0, though we'll just have to fail the probe in that case, but at least it avoids a division by zero. Sashiko: > Could this cause a regression where the PWM output is left in a > broken state if the hardware resets the DEPTH field to 0? The hardware reset value for the field is 256, so that is not the case. The other item is a pre-existing issue. Worth fixing, but not necessarily in the purview of this feature. I can respin to add the clk_rate =3D=3D 0 check. Cheers Mikko