Re: [PATCH 4/5] riscv: dts: add initial canmv-k230 and k230-evb dts

[Yangyu Chen <cyy@cyyself.name>]

On 2024/3/5 03:00, Conor Dooley wrote:
> Hey,
> 
> Meant to reply here earlier but I got distracted.
> 
> On Sun, Mar 03, 2024 at 09:26:26PM +0800, Yangyu Chen wrote:
>> Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte
>> K230 SoC [1].
>>
>> Some key considerations:
>> - Only enable BigCore which is 1.6GHz RV64GCBV
>>
>> Since is there cache coherence between two cores remains a mystery since
>> they have a dedicated L2 Cache. And the factory SDK uses it for other OS
>> by default.
>>
>> Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is
>> CPU1, the csr.mhartid of this core is 0.
>>
>> - Support for "zba" "zbb" "zbc" "zbs" are tested by hand
>>
>> The user manual of C908 from T-Head does not document it specifically.
>> It just said it supports B extension V1.0-rc1. [2]
>>
>> - Support for "zicbom" is tested by hand
>>
>> Have tested with some out-of-tree drivers that need DMA and they do not
>> come to the dts currently.
>>
>> - Cache parameters are inferred from T-Head docs [2] and Cannan docs [1]
>>
>> L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline
>> L2: 256KB, PIPI 16-way set-associative, 64B Cacheline
>>
>> The numbers of cache sets are calculated from these parameters.
>>
>> - MMU only supports Sv39
>>
>> Since T-Head docs [2] says C908 should support sv48. However, it will fail
>> during the kernel probe. I also tested it by hand on M-Mode software,
>> writing sv48 to satp.mode will not trap but will leave the csr unchanged.
>>
>> [1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction
>> [2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf
>>
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>> ---
>>   arch/riscv/boot/dts/canaan/Makefile       |   2 +
>>   arch/riscv/boot/dts/canaan/canmv-k230.dts |  23 ++++
> 
> Could you name this file "k230-canmv.dts" please, so that the soc comes
> first?
> 

OK. For patch v3.

>>   arch/riscv/boot/dts/canaan/k230-evb.dts   |  23 ++++
>>   arch/riscv/boot/dts/canaan/k230.dtsi      | 146 ++++++++++++++++++++++
>>   4 files changed, 194 insertions(+)
>>   create mode 100644 arch/riscv/boot/dts/canaan/canmv-k230.dts
>>   create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
>>   create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
>> index 987d1f0c41f0..b4a0ec668f9a 100644
>> --- a/arch/riscv/boot/dts/canaan/Makefile
>> +++ b/arch/riscv/boot/dts/canaan/Makefile
>> @@ -5,3 +5,5 @@ dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
>>   dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
>>   dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
>>   dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maixduino.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
>> +dtb-$(CONFIG_ARCH_CANAAN) += canmv-k230.dtb
>> \ No newline at end of file
>> diff --git a/arch/riscv/boot/dts/canaan/canmv-k230.dts b/arch/riscv/boot/dts/canaan/canmv-k230.dts
>> new file mode 100644
>> index 000000000000..09777616d30e
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/canaan/canmv-k230.dts
>> @@ -0,0 +1,23 @@
>> +// SPDX-License-Identifier: GPL-2.0+
> 
> Is there a reason that you only put these under GPL-2.0+?
> The usual license for DT stuff is (GPL-2.0 OR BSD-2-Clause), dual
> licensing makes it easier for other projects to use the devicetrees.
> 

No. Just choose the same license from K210. I will change to both 
GPL-2.0 or BSD-2-Caluse on patchv3.

>> +
>> +		plic: interrupt-controller@f00000000 {
>> +			compatible = "thead,c900-plic";
>> +			reg = <0xf 0x00000000 0x0 0x04000000>;
>> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
>> +			interrupt-controller;
>> +			reg-names = "control";
>> +			#address-cells = <0>;
>> +			#interrupt-cells = <2>;
>> +			riscv,ndev = <208>;
>> +		};
>> +
>> +		clint: timer@f04000000 {
>> +			compatible = "thead,c900-clint";
>> +			reg = <0xf 0x04000000 0x0 0x04000000>;
>> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>> +		};
> 
> Both of these should have SoC-specific compatibles. Without them, this
> should not pass dtbs_check. Did you run it?
> 

Sorry. I haven't run it before submitting patch v1. But I have run it 
and got something fixed on patchv2.

> Cheers,
> Conor.
> 

To be honest, I want some review comments on the CPU node. As we know 
K230 is a dual-core soc. But I didn't know the details of the bus, even 
for is there was cache coherence between two cores. The factory SDK also 
provides a linux dts having only one core. I don't know whether it is 
acceptable.