From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7289E227E95 for ; Tue, 15 Jul 2025 12:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752583691; cv=none; b=d+wSL5Yrd0zKBTJL9s1HvlrzXyPUJ1pKmhWD6qsPfkTTWQbjT2laCgrfpmkffR63bC24W4YQXMrjx0Z78n3KV2QPl46ZSwMJkmHQ6tCmTVcta1Sg4Djc9RuW9FSWN7+gVvL0K6yao603J5eX7xvapCrh5mzqT9u9MNlccbe5Jn8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752583691; c=relaxed/simple; bh=EPw4dQ8dfonq0P3aVNF8vSgP2GKEr/WhL3SjzkV20GA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=GLqrGMPbUPUOeQ2MpKZoBmMZU+U/x9tJGcETI0hoDCz7PSZSue07zKHsHg+h4cVS0SEkx2VtEMrV2pKtEYUYW29R/7VnaeXpyop6iG3g9eg0v/HIK797vE8BGkYUtD0XoFrVoyDb/sUPyHsznDgx+2wpmInYT2+LJgH9gdM/lCI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=qB0U8wgK; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qB0U8wgK" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4561ca74829so18691675e9.0 for ; Tue, 15 Jul 2025 05:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752583686; x=1753188486; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=Iqo4mhXycGD6rw4UTAUbadK3TxDOKrzOub9ByVVv0xc=; b=qB0U8wgKfVafmrdK4SZntgzOzE/kz1dySTTGLPRY+cRfUl+WrBt/VwC2m6FYNU1yH7 Vh5BLKy73qAclnLkaZjE/fXOjsRaiS/LP4k3CVN1eFuAAlmSk98KJ6ARpQwnDoA7xveM OoqV1+X1vjz/ioplbVCKh6qNdpaOY8hji45gbqObDErGAKeuEh8ysJKs8m1bschPqrf/ owuYOAwLVuJPWGHB7ULe4Co9G7QC+wuMLsztuA5lc2PoBFbi1ZzJut1uySvsfMELl3sQ OGr+fmEXoAxqLkign944o2Adn8eacojfmhP7KQ/K+B0S3jc9f1fu06kOC4VgvsogcF64 RwAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752583686; x=1753188486; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Iqo4mhXycGD6rw4UTAUbadK3TxDOKrzOub9ByVVv0xc=; b=wjlGQIDYAT8x2bdmky+oY0MynA9lS01XrSvPRQMeKbdjQyYLERHCTPlIos6RP2i2Hm LOb6n5s6w0eh39niyjKd+T64BSSxlolgQUvRHD/fpNXiBGGBrUy+cBn70THeTKXyyLHu WqH9589TpNj6zIQ450vwmHVUYxBOiq/e6U9QS/5xOsHwE+Pg7bp2m+beRt3LgYXu2XUR Jo7kZEMv85wpyWtG+9qXEwAlLHxP9TOuJxGQ+lb6sbGAu3kU8oobxglFukXonkuWHkaB 7TyZL6NPhKFMWUncB1E9F9J53eg/pLiF+1Ha2A7TCcGFfwHT1Zmipaw3zdSyLQB4AjIs FnCA== X-Forwarded-Encrypted: i=1; AJvYcCUM9/g5ytRu5dZ5ALH3u7m1X3GSmN3t5RJMU/FkFDIXUXXUhmhxorSZW/bvEYjyFOwgNd0s2+34/F0=@vger.kernel.org X-Gm-Message-State: AOJu0YyJob0O+TZsmBg2o1OU7VIp/G9LPSBnHVNo6NO5T+tUkJYt2f92 tPkl8dSsMPOvfU+8kygQW/MNFCEjNN9AsZUvsWLsrInpieKBZvsZqhTxf/AIjl/dlQg= X-Gm-Gg: ASbGncvD2nq4Ym0GMVh1HNlYnD33MQrWnA7yvPdvr5K4zuBGX4xNjuWDnboP06CV9E0 iDktQTknRCtQfstLP6koN2F6TDvt2pTtYCW8P5AO0YDtphQ+jHLK9FLz3argrwll7XbS1BNXfNx 2HfEYyx5Yp8ldu0y26br6rQzNYZqlOjVIPNIO28AycXjFn+NRtoitPsF89OK+RqIexTXueNfvUD dIKfmqTbBbupz6bU/v6BJVRmWfAAltATWIPg8SrrblSwjeKSuI9hmUNbvVPoEj5dBqCcHlGlNPu IIwvGpcnGM7649bKRs5Hxq9TZtsKCLZQF8jld3wQPzUbLq6BHp8FmedFuARn25l9Xvs8b4qo6K7 e3dvvIAdaqUIyTOHRbG6x7sXzKfs= X-Google-Smtp-Source: AGHT+IHksQQexPF9xeIAPmAN5RQVQtwJAwRE0OCzaS0bMryNoBsPAdHpgVxKs40ogsxaKO2X4QSDVw== X-Received: by 2002:a05:600c:8483:b0:440:6a1a:d89f with SMTP id 5b1f17b1804b1-455bd87a4a2mr140606855e9.4.1752583685607; Tue, 15 Jul 2025 05:48:05 -0700 (PDT) Received: from [192.168.1.3] ([185.48.76.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45610c518e9sm84882505e9.17.2025.07.15.05.48.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 05:48:05 -0700 (PDT) Message-ID: <04d52182-6043-4eaf-a898-9f8ccc893e5f@linaro.org> Date: Tue, 15 Jul 2025 13:48:03 +0100 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/10] arm64/boot: Enable EL2 requirements for SPE_FEAT_FDS To: Will Deacon Cc: Catalin Marinas , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , leo.yan@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev References: <20250605-james-perf-feat_spe_eft-v3-0-71b0c9f98093@linaro.org> <20250605-james-perf-feat_spe_eft-v3-4-71b0c9f98093@linaro.org> Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/07/2025 2:54 pm, Will Deacon wrote: > On Thu, Jun 05, 2025 at 11:49:02AM +0100, James Clark wrote: >> SPE data source filtering (optional from Armv8.8) requires that traps to >> the filter register PMSDSFR be disabled. Document the requirements and >> disable the traps if the feature is present. >> >> Tested-by: Leo Yan >> Signed-off-by: James Clark >> --- >> Documentation/arch/arm64/booting.rst | 11 +++++++++++ >> arch/arm64/include/asm/el2_setup.h | 14 ++++++++++++++ >> 2 files changed, 25 insertions(+) >> >> diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst >> index dee7b6de864f..abd75085a239 100644 >> --- a/Documentation/arch/arm64/booting.rst >> +++ b/Documentation/arch/arm64/booting.rst >> @@ -404,6 +404,17 @@ Before jumping into the kernel, the following conditions must be met: >> - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. >> - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. >> >> + For CPUs with SPE data source filtering (FEAT_SPE_FDS): >> + >> + - If EL3 is present: >> + >> + - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1. >> + >> + - If the kernel is entered at EL1 and EL2 is present: >> + >> + - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. >> + - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. >> + >> For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): >> >> - If the kernel is entered at EL1 and EL2 is present: >> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h >> index 1e7c7475e43f..02b4a7fc016e 100644 >> --- a/arch/arm64/include/asm/el2_setup.h >> +++ b/arch/arm64/include/asm/el2_setup.h >> @@ -279,6 +279,20 @@ >> orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 >> orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 >> .Lskip_pmuv3p9_\@: >> + mrs x1, id_aa64dfr0_el1 >> + ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 >> + /* If SPE is implemented, */ >> + cmp x1, #ID_AA64DFR0_EL1_PMSVer_IMP >> + b.lt .Lskip_spefds_\@ >> + /* we can read PMSIDR and */ >> + mrs_s x1, SYS_PMSIDR_EL1 >> + and x1, x1, #PMSIDR_EL1_FDS >> + /* if FEAT_SPE_FDS is implemented, */ >> + cbz x1, .Lskip_spefds_\@ >> + /* disable traps to PMSDSFR. */ >> + orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1 > > Why is this being done here rather than alongside the existing SPE > configuration of HDFGRTR_EL2 and HDFGWTR_EL2 near the start of > __init_el2_fgt? > > Will I thought everything was separated by which trap configs it writes to, rather than the feature. This SPE feature is in HDFGRTR2 so I put it in __init_el2_fgt2 rather than __init_el2_fgt. I suppose we could have a single __init_el2_spe that writes to both HDFGRTR and HDFGRTR2 but we'd have to be careful to not overwrite what was already done in the other sections.