From: "Andy Lutomirski" <luto@kernel.org>
To: "H. Peter Anvin" <hpa@zytor.com>,
"Dave Hansen" <dave.hansen@intel.com>,
"Rick P Edgecombe" <rick.p.edgecombe@intel.com>,
"Sohil Mehta" <sohil.mehta@intel.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"the arch/x86 maintainers" <x86@kernel.org>,
"Dave Hansen" <dave.hansen@linux.intel.com>
Cc: "Jonathan Corbet" <corbet@lwn.net>,
"Ard Biesheuvel" <ardb@kernel.org>,
"david.laight.linux@gmail.com" <david.laight.linux@gmail.com>,
"jpoimboe@kernel.org" <jpoimboe@kernel.org>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Tony Luck" <tony.luck@intel.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Kirill A . Shutemov" <kas@kernel.org>,
"Sean Christopherson" <seanjc@google.com>,
"Randy Dunlap" <rdunlap@infradead.org>,
"David Woodhouse" <dwmw@amazon.co.uk>,
"Vegard Nossum" <vegard.nossum@oracle.com>,
"Xin Li" <xin@zytor.com>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"Kees Cook" <kees@kernel.org>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
"linux-efi@vger.kernel.org" <linux-efi@vger.kernel.org>,
"Geert Uytterhoeven" <geert@linux-m68k.org>
Subject: Re: [PATCH v10 08/15] x86/vsyscall: Reorganize the page fault emulation code
Date: Thu, 30 Oct 2025 10:35:09 -0700 [thread overview]
Message-ID: <0630921a-a99f-4577-bc8e-0aaf08b3175d@app.fastmail.com> (raw)
In-Reply-To: <E95F62DC-0B5D-47ED-8B72-F619B45340C8@zytor.com>
On Thu, Oct 30, 2025, at 10:22 AM, H. Peter Anvin wrote:
> On October 30, 2025 9:58:02 AM PDT, Andy Lutomirski <luto@kernel.org> wrote:
>>
>>
>>On Tue, Oct 7, 2025, at 11:48 AM, Dave Hansen wrote:
>>> On 10/7/25 11:37, Edgecombe, Rick P wrote:
>>>>> /*
>>>>> * No point in checking CS -- the only way to get here is a user mode
>>>>> * trap to a high address, which means that we're in 64-bit user code.
>>>> I don't know. Is this as true any more? We are now sometimes guessing based on
>>>> regs->ip of a #GP. What if the kernel accidentally tries to jump to the vsyscall
>>>> address? Then we are reading the kernel stack and strange things. Maybe it's
>>>> worth replacing the comment with a check? Feel free to call this paranoid.
>>>
>>> The first check in emulate_vsyscall() is:
>>>
>>> /* Write faults or kernel-privilege faults never get fixed up. */
>>> if ((error_code & (X86_PF_WRITE | X86_PF_USER)) != X86_PF_USER)
>>> return false;
>>>
>>> If the kernel jumped to the vsyscall page, it would end up there, return
>>> false, and never reach the code near the "No point in checking CS" comment.
>>>
>>> Right? Or am I misunderstanding the scenario you're calling out?
>>>
>>> If I'm understanding it right, I'd be a bit reluctant to add a CS check
>>> as well.
>>
>>IMO it should boil down to exactly the same thing as the current code for the #PF case and, for #GP, there are two logical conditions that we care about:
>>
>>1. Are we in user mode?
>>
>>2. Are we using a 64-bit CS such that vsyscall emulation makes sense.
>>
>>Now I'd be a tiny bit surprised if a CPU allows you to lretq or similar to a 32-bit CS with >2^63 RIP, but what do I know? One could test this on a variety of machines, both Intel and AMD, to see what actually happens.
>>
>>But the kernel wraps all this up as user_64bit_mode(regs). If user_64bit_mode(regs) is true and RIP points to a vsyscall, then ISTM there aren't a whole lot of options. Somehow we're in user mode, either via an exit from kernel mode or via CALL/JMP/whatever from user mode, and RIP is pointing at the vsyscall page, and CS is such that, in the absence of LASS, we would execute the vsyscall. I suppose the #GP could be from some other cause than a LASS violation, but that doesn't seem worth worrying about.
>>
>>So I think all that's needed is to update "[PATCH v10 10/15] x86/vsyscall: Add vsyscall emulation for #GP" to check user_64bit_mode(regs) for the vsyscall case. (As submitted, unless I missed something while composing the patches in my head, it's only checking user_mode(regs), and I think it's worth the single extra line of code to make the result a tiny bit more robust.)
>
> user_64bit_mode() is a CS check :)
>
> There is that one extra check for PARAVIRT_XXL that *could* be gotten
> rid of by making the PV code report its 64-bit selector and patching it
> into the test, but it is on the error path anyway...
In the hopefully unlikely event that anyone cares about #GP performance, they should probably care far, far more about the absurd PASID fix up than anything else :)
next prev parent reply other threads:[~2025-10-30 17:35 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-07 6:51 [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 01/15] x86/cpu: Enumerate the LASS feature bits Sohil Mehta
2025-10-07 18:19 ` Edgecombe, Rick P
2025-10-07 18:28 ` Dave Hansen
2025-10-07 20:20 ` Sohil Mehta
2025-10-07 20:38 ` Edgecombe, Rick P
2025-10-07 20:53 ` Sohil Mehta
2025-10-16 3:10 ` H. Peter Anvin
2025-10-07 20:49 ` Sohil Mehta
2025-10-07 23:16 ` Xin Li
2025-10-08 16:00 ` Edgecombe, Rick P
2025-10-16 15:35 ` Borislav Petkov
2025-10-21 18:03 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 02/15] x86/asm: Introduce inline memcpy and memset Sohil Mehta
2025-10-21 12:47 ` Borislav Petkov
2025-10-21 13:48 ` David Laight
2025-10-21 18:06 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 03/15] x86/alternatives: Disable LASS when patching kernel alternatives Sohil Mehta
2025-10-07 16:55 ` Edgecombe, Rick P
2025-10-07 22:28 ` Sohil Mehta
2025-10-08 16:22 ` Edgecombe, Rick P
2025-10-10 17:10 ` Sohil Mehta
2025-10-21 20:03 ` Borislav Petkov
2025-10-21 20:55 ` Sohil Mehta
2025-10-22 9:56 ` Borislav Petkov
2025-10-22 19:49 ` Sohil Mehta
2025-10-22 20:03 ` Luck, Tony
2025-10-22 8:25 ` Peter Zijlstra
2025-10-22 9:40 ` Borislav Petkov
2025-10-22 10:22 ` Peter Zijlstra
2025-10-22 10:52 ` Borislav Petkov
2025-10-07 6:51 ` [PATCH v10 04/15] x86/cpu: Set LASS CR4 bit as pinning sensitive Sohil Mehta
2025-10-07 18:24 ` Edgecombe, Rick P
2025-10-07 23:11 ` Sohil Mehta
2025-10-08 16:52 ` Edgecombe, Rick P
2025-10-10 19:03 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 05/15] x86/cpu: Defer CR pinning enforcement until late_initcall() Sohil Mehta
2025-10-07 17:23 ` Edgecombe, Rick P
2025-10-07 23:05 ` Sohil Mehta
2025-10-08 17:36 ` Edgecombe, Rick P
2025-10-10 20:45 ` Sohil Mehta
2025-10-15 21:17 ` Sohil Mehta
2025-10-17 19:28 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 06/15] x86/efi: Disable LASS while mapping the EFI runtime services Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 07/15] x86/kexec: Disable LASS during relocate kernel Sohil Mehta
2025-10-07 17:43 ` Edgecombe, Rick P
2025-10-07 22:33 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 08/15] x86/vsyscall: Reorganize the page fault emulation code Sohil Mehta
2025-10-07 18:37 ` Edgecombe, Rick P
2025-10-07 18:48 ` Dave Hansen
2025-10-07 19:53 ` Edgecombe, Rick P
2025-10-07 22:52 ` Sohil Mehta
2025-10-08 17:42 ` Edgecombe, Rick P
2025-10-30 16:58 ` Andy Lutomirski
2025-10-30 17:22 ` H. Peter Anvin
2025-10-30 17:35 ` Andy Lutomirski [this message]
2025-10-30 19:28 ` Sohil Mehta
2025-10-30 21:37 ` David Laight
2025-10-07 6:51 ` [PATCH v10 09/15] x86/traps: Consolidate user fixups in exc_general_protection() Sohil Mehta
2025-10-07 17:46 ` Edgecombe, Rick P
2025-10-07 22:41 ` Sohil Mehta
2025-10-08 17:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 10/15] x86/vsyscall: Add vsyscall emulation for #GP Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 11/15] x86/vsyscall: Disable LASS if vsyscall mode is set to EMULATE Sohil Mehta
2025-10-07 18:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 12/15] x86/traps: Communicate a LASS violation in #GP message Sohil Mehta
2025-10-07 18:07 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 13/15] x86/traps: Generalize #GP address decode and hint code Sohil Mehta
2025-10-07 18:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 14/15] x86/traps: Provide additional hints for a kernel stack segment fault Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 15/15] x86/cpu: Enable LASS by default during CPU initialization Sohil Mehta
2025-10-07 18:42 ` Edgecombe, Rick P
2025-10-07 16:23 ` [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Edgecombe, Rick P
2025-10-17 19:52 ` Sohil Mehta
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