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[131.111.5.141]) by smtp.gmail.com with ESMTPSA id d9sm11550737wre.52.2021.11.23.03.53.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Nov 2021 03:53:49 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [RFC PATCH 2/3] riscv: Add early_param to decrease firmware region From: Jessica Clarke In-Reply-To: Date: Tue, 23 Nov 2021 11:53:48 +0000 Cc: Guo Ren , Palmer Dabbelt , atishp@rivosinc.com, "linux-kernel@vger.kernel.org List" , linux-riscv , Linux Doc Mailing List , Guo Ren , Anup Patel , Alexandre Ghiti , Alexandre Ghiti Content-Transfer-Encoding: quoted-printable Message-Id: <07AD2CEA-3C9B-48FA-8E67-3B60448A08F0@jrtc27.com> References: <20211123015717.542631-1-guoren@kernel.org> <20211123015717.542631-3-guoren@kernel.org> To: Anup Patel X-Mailer: Apple Mail (2.3654.120.0.1.13) Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On 23 Nov 2021, at 03:44, Anup Patel wrote: >=20 > +Alex >=20 > On Tue, Nov 23, 2021 at 7:27 AM wrote: >>=20 >> From: Guo Ren >>=20 >> Using riscv.fw_size in cmdline to tell the kernel what the >> firmware (opensbi) size is. Then reserve the proper size of >> firmware to save memory instead of the whole 2MB. It's helpful >> to satisfy a small memory system (D1s/F133 from Allwinner). >>=20 >> Signed-off-by: Guo Ren >> Cc: Palmer Dabbelt >> Cc: Anup Patel >> Cc: Atish Patra >> --- >> arch/riscv/mm/init.c | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >>=20 >> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c >> index 920e78f8c3e4..f7db6d40213d 100644 >> --- a/arch/riscv/mm/init.c >> +++ b/arch/riscv/mm/init.c >> @@ -159,6 +159,15 @@ static int __init early_mem(char *p) >> } >> early_param("mem", early_mem); >>=20 >> +static phys_addr_t firmware_size __initdata; >> +static int __init early_get_firmware_size(char *arg) >> +{ >> + firmware_size =3D memparse(arg, &arg); >> + >> + return 0; >> +} >> +early_param("riscv.fwsz", early_get_firmware_size); >> + >=20 > We have avoided any RISC-V specific kernel parameter till now > and I don't think adding "riscv.fwsz" is the right approach. >=20 > OpenSBI adds a reserved memory node (mmode_resv@8000000) > to mark the memory where it is running as reserved. In fact, all > M-mode runtime firmware should be adding a reserved memory > node just like OpenSBI. BBL does not do this and, even if it=E2=80=99s modified today, older = versions will still need to be supported for quite a while longer. In FreeBSD[1] we only reserve the first 2 MiB of DRAM (we don=E2=80=99t = care about RV32) if there is no reserved memory node covering the DRAM base address, which avoids this issue. The only downside with that approach is that if firmware occupies a different region than the beginning of DRAM (or there is no firmware resident in the supervisor=E2=80=99s = physical address space, as is the case for a virtualised guest) then it unnecessarily reserves that first 2 MiB, but that=E2=80=99s not a huge = deal, and can=E2=80=99t be avoided so long as BBL continues to exist (well, I = guess you could probe the SBI implementation ID if you really cared about that, but I=E2=80=99ve yet to hear of a platform where the SBI = implementation, if it exists, isn=E2=80=99t at the start of DRAM, and if you=E2=80=99re = virtualising then you probably have enough DRAM that you don=E2=80=99t notice 2 MiB = going missing). Jess [1] = https://github.com/freebsd/freebsd-src/blob/main/sys/riscv/riscv/machdep.c= #L554-L568