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AJvYcCWVyfI1BeXVegpFMZEojJyyQmqmx9Np0Acl66T7hKGoYQ7HIXENt2IkxfSkMzw6u0Z3boT3sPPS3j07iJhbz+9VNTVDeAMfuacR X-Gm-Message-State: AOJu0Yz/iyyZUDXuRySqmkYomfd/qAEK03Z75idyd/zcki+I5YHoRmLP XlgXBuxCzdQ5NjsEQ8KNjICPUabmXsjO1vxyCTxSOTE6IBddz0vwsi91tyirzZk= X-Google-Smtp-Source: AGHT+IH5OdYzcnTJ6D+zS8aIAAaJJTXjxs59RqwCSCJ2ph2wWmR2x/JtfntC1ryqtH5pn476yLkmFg== X-Received: by 2002:a05:6512:3baa:b0:52c:8ea3:1aea with SMTP id 2adb3069b0e04-52c8ea31d06mr2106714e87.34.1718041927588; Mon, 10 Jun 2024 10:52:07 -0700 (PDT) Received: from smtpclient.apple ([131.111.5.201]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35f2598ac1esm2762915f8f.93.2024.06.10.10.52.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Jun 2024 10:52:07 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.500.171.1.1\)) Subject: Re: [PATCH 05/13] riscv: vector: Use vlenb from DT for thead From: Jessica Clarke In-Reply-To: <20240609-xtheadvector-v1-5-3fe591d7f109@rivosinc.com> Date: Mon, 10 Jun 2024 18:51:56 +0100 Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <0944414F-321F-4159-AB85-C4B66AE9550B@jrtc27.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> <20240609-xtheadvector-v1-5-3fe591d7f109@rivosinc.com> To: Charlie Jenkins X-Mailer: Apple Mail (2.3774.500.171.1.1) On 10 Jun 2024, at 05:45, Charlie Jenkins wrote: >=20 > If thead,vlenb is provided in the device tree, prefer that over = reading > the vlenb csr. >=20 > Signed-off-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 2 ++ > arch/riscv/kernel/cpufeature.c | 48 = +++++++++++++++++++++++++++++++++++++ > arch/riscv/kernel/vector.c | 12 +++++++++- > 3 files changed, 61 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/riscv/include/asm/cpufeature.h = b/arch/riscv/include/asm/cpufeature.h > index b029ca72cebc..e0a3164c7a06 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, = riscv_cpuinfo); > /* Per-cpu ISA extensions. */ > extern struct riscv_isainfo hart_isa[NR_CPUS]; >=20 > +extern u32 thead_vlenb_of; > + > void riscv_user_isa_enable(void); >=20 > #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, = _subset_exts_size) { \ > diff --git a/arch/riscv/kernel/cpufeature.c = b/arch/riscv/kernel/cpufeature.c > index 2107c59575dd..0c01f33f2348 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) = __read_mostly; > /* Per-cpu ISA extensions. */ > struct riscv_isainfo hart_isa[NR_CPUS]; >=20 > +u32 thead_vlenb_of; > + > /** > * riscv_isa_extension_base() - Get base extension word > * > @@ -625,6 +627,46 @@ static void __init riscv_fill_vendor_ext_list(int = cpu) > } > } >=20 > +static int has_thead_homogeneous_vlenb(void) > +{ > + int cpu; > + u32 prev_vlenb =3D 0; > + u32 vlenb; > + > + /* Ignore vlenb if vector is not enabled in the kernel */ > + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) It=E2=80=99s not V though. You probably want to split out =E2=80=9Cvector=E2= =80=9D from =E2=80=9CV=E2=80=9D in Kconfig land. Most places want the former, I assume, but some want the latter. Jess > + return 0; > + > + for_each_possible_cpu(cpu) { > + struct device_node *cpu_node; > + > + cpu_node =3D of_cpu_device_node_get(cpu); > + if (!cpu_node) { > + pr_warn("Unable to find cpu node\n"); > + return -ENOENT; > + } > + > + if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { > + of_node_put(cpu_node); > + > + if (prev_vlenb) > + return -ENOENT; > + continue; > + } > + > + if (prev_vlenb && vlenb !=3D prev_vlenb) { > + of_node_put(cpu_node); > + return -ENOENT; > + } > + > + prev_vlenb =3D vlenb; > + of_node_put(cpu_node); > + } > + > + thead_vlenb_of =3D vlenb; > + return 0; > +} > + > static int __init riscv_fill_hwcap_from_ext_list(unsigned long = *isa2hwcap) > { > unsigned int cpu; > @@ -689,6 +731,12 @@ static int __init = riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) > riscv_fill_vendor_ext_list(cpu); > } >=20 > + if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, = XTHEADVECTOR) && > + has_thead_homogeneous_vlenb() < 0) { > + pr_warn("Unsupported heterogeneous vlenb detected, vector extension = disabled.\n"); > + elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; > + } > + > if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) > return -ENOENT; >=20 > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c > index 6727d1d3b8f2..3ba2f2432483 100644 > --- a/arch/riscv/kernel/vector.c > +++ b/arch/riscv/kernel/vector.c > @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) > { > unsigned long this_vsize; >=20 > - /* There are 32 vector registers with vlenb length. */ > + /* > + * There are 32 vector registers with vlenb length. > + * > + * If the thead,vlenb property was provided by the firmware, use that > + * instead of probing the CSRs. > + */ > + if (thead_vlenb_of) { > + this_vsize =3D thead_vlenb_of * 32; > + return 0; > + } > + > riscv_v_enable(); > this_vsize =3D csr_read(CSR_VLENB) * 32; > riscv_v_disable(); >=20 > --=20 > 2.44.0 >=20 >=20 > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv