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Wed, 19 Aug 2026 06:26:34 -0700 (PDT) X-Received: by 2002:a05:6a21:110:b0:3b4:661d:8405 with SMTP id adf61e73a8af0-3cd00c6d745mr6159988637.4.1787145993729; Wed, 19 Aug 2026 06:26:33 -0700 (PDT) Received: from [10.219.56.166] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc155689110sm598347a12.22.2026.08.19.06.26.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Aug 2026 06:26:33 -0700 (PDT) Message-ID: <10349e29-b583-403f-a89a-9a00c73666bc@oss.qualcomm.com> Date: Wed, 19 Aug 2026 18:56:23 +0530 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 00/15] accel/qda: Qualcomm DSP Accelerator driver To: Krzysztof Kozlowski , Oded Gabbay , Jonathan Corbet , Shuah Khan , Randy Dunlap , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: Bharath Kumar , Chenna Kesava Raju , srinivas.kandagatla@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-arm-msm@vger.kernel.org, llvm@lists.linux.dev, iommu@lists.linux.dev, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org References: <20260817-qda-v2-v2-0-69a02e9090d4@oss.qualcomm.com> <3322b42b-3755-45ec-ad55-345125f0d488@kernel.org> Content-Language: en-US From: Ekansh Gupta In-Reply-To: <3322b42b-3755-45ec-ad55-345125f0d488@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: PfS37b4qsl3g-wAaMNvs69maRYvZ6G17 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE5MDEwNCBTYWx0ZWRfX7jB0nhhfx1lb cT7U5nl9Zfl+CHGZgLt+tlR/uOh84JLexVRU6MCaNvV07J65OTipZqxLiWQcOkpPbjgZeCihoCe z0pypwZmDmrgcDphCUr3NrLylpBgNAA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE5MDEwNCBTYWx0ZWRfX5fXJe74AHF4u VnMwISrISbbPDTZ9eunk+scUGyWbRlouubifjTeOhBfzYGoxzC5MUislQ0EOEe+h/TsnrSS1P8Q VkchwIG0URRSHA5iZuIPUUGCCTlxZYAv7c4EpiZOnNOTaPY8ZScAa8+fnGdot3o9nLpJ4CWjg7f crnQvXHrkrLyD0YVFFT9GVAQlCuoczPN6CmU0moOk9pnZySOVsLSoTdYQrMHbOxFhynIr1z8rJJ 3OpjnZK8CLaHQtcn0wr7WO8ZMSKBtae2PrxttHtX+G+Bwsu4C+2HeQLQ6a2ogHZwxo8/zbNe12j a9SNiu7CQhwCV//EHOcb/Uai9h30FC8c9oHmPtFJRV+GKEdPv0qakBj7GGFOi+4AzrnWlzYtTOp 3ZUfy4vTuEpsnev6+B72jA/dtMOl/GAXxL0K+yOQEkAM9I3Xr7jyh+3Az2HmGpoj37VNvmwJ9sA zflCYaJjNnLlEv+yMRQ== X-Authority-Analysis: v=2.4 cv=aNrAb79m c=1 sm=1 tr=0 ts=6a85af0b cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=1aprj6cQADeN8GqOYRYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: PfS37b4qsl3g-wAaMNvs69maRYvZ6G17 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_03,2026-08-19_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608190104 On 19-08-2026 00:43, Krzysztof Kozlowski wrote: > On 17/08/2026 06:47, Ekansh Gupta wrote: >> This patch series introduces the Qualcomm DSP Accelerator (QDA) driver, >> a DRM-based accelerator driver for Qualcomm DSPs. The driver provides a >> standardized interface for offloading computational tasks to DSPs found >> on Qualcomm SoCs, supporting all DSP domains. >> >> The QDA driver implements the FastRPC protocol over the DRM accel >> subsystem. It uses the same device-tree node structure as the existing >> fastrpc driver in drivers/misc/. The approach for binding the QDA driver >> to device-tree nodes while coexisting with the fastrpc driver is an open >> item described below. > > No. Grow/replace/improve existing driver instead of coming with a duplicate. > > That's a standard upstream requirement, basically given on every > upstreaming guide. > > Please watch old talk from Greg - "I Don’t Want Your Code!". Posted discussion threads here[1]. Would seek comments from Dmitry, Srini as well. [1] https://lore.kernel.org/all/3476b5c3-7983-4994-a901-3d7d8bd75255@oss.qualcomm.com/ > >> >> v1: https://lore.kernel.org/all/20260519-qda-series-v1-0-b2d984c297f8@oss.qualcomm.com/ >> RFC: https://lore.kernel.org/dri-devel/20260224-qda-firstpost-v1-0-fe46a9c1a046@oss.qualcomm.com/T/ >> >> Changes since v1 >> ================ >> >> The v1 review raised two architectural objections and one correctness >> issue; all three are resolved in v2: >> >> * Christian König (dma-buf maintainer) pointed out that the imported- >> buffer path silently assumed the IOMMU maps every buffer as a single >> contiguous range, which is not guaranteed. v2 walks the scatterlist >> and cleanly rejects non-contiguous imports; contiguous imports (e.g. >> CMA DMA-buf heap) are accepted. (patch 11) >> >> * Dmitry Baryshkov objected to three different buffer-passing formats >> in the invoke IOCTL (DMA-BUF fd, direct/inline, DMA handle). v2 >> passes only GEM handles; userspace imports any fd to a GEM handle >> with DRM_IOCTL_PRIME_FD_TO_HANDLE before invoking. Packing and >> overlap handling are left to userspace. (patch 12) >> >> * The memory manager (patch 07) used a fixed 16-entry array without >> justification and leaked the device descriptor on teardown. v2 >> allocates the array from the DT context-bank count (as Dmitry >> suggested) and frees it correctly. >> >> User-space staging branch >> ========================= >> https://github.com/qualcomm/fastrpc/tree/accel/staging >> >> Key Features >> ============ >> >> * Standard DRM accelerator interface via /dev/accel/accelN >> * GEM-based buffer management with DMA-BUF import (PRIME) >> * IOMMU-based memory isolation using per-process context banks >> * FastRPC protocol implementation for DSP communication >> * RPMsg transport layer for reliable message passing >> * Support for all DSP domains (ADSP, CDSP, SDSP, GDSP) >> * DRM IOCTL interface for DSP session management, buffer allocation, >> and remote procedure invocation >> >> Architecture >> ============ >> >> 1. DRM Accelerator Framework Integration >> The driver registers as a DRM accel device, exposing a standard >> /dev/accel/accelN character device node. This provides established >> DRM infrastructure for device management, file operations, and >> IOCTL dispatch. >> >> 2. Memory Management >> Buffers are managed as GEM objects with PRIME support for DMA-BUF >> import. This enables buffer sharing with other DRM drivers (GPU, >> camera, video) using standard kernel mechanisms. Only contiguous >> imports are accepted; the driver verifies contiguity at import time >> rather than assuming it. >> >> 3. IOMMU Context Bank Management >> IOMMU context banks (CBs) are represented as proper struct device >> instances on a custom virtual bus (qda-compute-cb). Each CB device >> is registered with the IOMMU subsystem and receives its own IOMMU >> domain, enabling per-session address space isolation. The custom >> bus was introduced because IOMMU context banks are synthetic >> constructs — not real platform devices — and to ensure CB device >> lifetime is strictly subordinate to the parent QDA device. >> See also: https://lore.kernel.org/all/245d602f-3037-4ae3-9af9-d98f37258aae@oss.qualcomm.com/ >> >> 4. Memory Manager Architecture >> The memory manager maintains a registry of IOMMU devices in an >> array sized to the number of context banks described in the device >> tree, and coordinates per-process device assignment with reference- >> counted lifetime management. The DMA-coherent backend allocates >> buffers with SID-prefixed DMA addresses for DSP firmware >> compatibility. >> >> 5. Transport Layer >> RPMsg communication is handled in a dedicated transport layer >> (qda_rpmsg.c), separate from the core DRM driver logic. >> >> 6. Code Organization >> The driver is organized across multiple files (~4800 lines total): >> * qda_drv.c: Core driver and DRM integration >> * qda_rpmsg.c: RPMsg transport layer >> * qda_cb.c: Context bank device management >> * qda_compute_bus.c: Custom virtual bus for CB devices >> * qda_gem.c: GEM object management >> * qda_prime.c: DMA-BUF import (PRIME) >> * qda_memory_manager.c: IOMMU device registry and allocation >> * qda_memory_dma.c: DMA-coherent allocation backend >> * qda_fastrpc.c: FastRPC protocol implementation >> * qda_ioctl.c: IOCTL dispatch >> >> 7. UAPI Design >> The driver exposes DRM-style IOCTLs defined in >> include/uapi/drm/qda_accel.h, following DRM UAPI conventions >> (__u32/__u64 types, C++ guard, GPL-2.0-only WITH Linux-syscall-note). >> Buffer arguments are identified by GEM handles; the driver never >> accepts DMA-BUF fds directly in any IOCTL. >> >> Patch Series Organization >> ========================== >> >> Patch 01: MAINTAINERS entry >> Patch 02: Driver documentation (Documentation/accel/qda/) >> Patches 03-04: Core driver skeleton and compute bus >> Patch 05: iommu: Register qda-compute-cb bus with IOMMU subsystem >> Patches 06-07: CB device enumeration and memory manager >> Patch 08: QUERY IOCTL and UAPI header >> Patches 09-11: GEM buffer management and PRIME import >> Patches 12-15: FastRPC protocol (invoke, session create/release, >> map/unmap) >> >> Open Items >> =========== >> >> 1. Device-Tree Compatible String >> The QDA driver uses the same device-tree node structure and >> properties as the existing fastrpc driver in drivers/misc/. A >> mechanism is needed to allow the QDA driver to bind to its device >> node independently of the fastrpc driver. >> >> The intended coexistence model is: platforms that require the >> complete fastrpc feature set continue to use "qcom,fastrpc"; new >> platforms where QDA's feature set is sufficient use a QDA-specific >> compatible string. New feature development is directed toward QDA. >> >> The options under consideration are: >> >> a) Add a new "qcom,qda" compatible string to the existing >> qcom,fastrpc.yaml binding, since the DT node structure and >> properties are identical. > No > >> >> b) Introduce a separate qcom,qda.yaml binding that references or >> inherits the fastrpc binding properties. > > No > >> >> Seeking guidance from DT binding maintainers on the preferred >> approach. > > Grow existing driver. You do not get new driver, you do not get new > bindings. > > > Best regards, > Krzysztof