From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-5.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham autolearn_force=no version=3.4.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id 4EB767D2EE for ; Thu, 30 Aug 2018 20:28:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727366AbeHaAbw (ORCPT ); Thu, 30 Aug 2018 20:31:52 -0400 Received: from mga09.intel.com ([134.134.136.24]:58621 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727207AbeHaAbv (ORCPT ); Thu, 30 Aug 2018 20:31:51 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Aug 2018 13:27:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,308,1531810800"; d="scan'208";a="259468619" Received: from 2b52.sc.intel.com ([143.183.136.52]) by fmsmga006.fm.intel.com with ESMTP; 30 Aug 2018 13:27:50 -0700 Message-ID: <1535660615.28258.37.camel@intel.com> Subject: Re: [RFC PATCH v3 12/24] x86/mm: Modify ptep_set_wrprotect and pmdp_set_wrprotect for _PAGE_DIRTY_SW From: Yu-cheng Yu To: Randy Dunlap , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , "Ravi V. Shankar" , Vedvyas Shanbhogue Date: Thu, 30 Aug 2018 13:23:35 -0700 In-Reply-To: <9879c17a-24da-d84a-5a7c-30bcbb473914@infradead.org> References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-13-yu-cheng.yu@intel.com> <9879c17a-24da-d84a-5a7c-30bcbb473914@infradead.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Thu, 2018-08-30 at 12:59 -0700, Randy Dunlap wrote: > On 08/30/2018 07:38 AM, Yu-cheng Yu wrote: > > > > When Shadow Stack is enabled, the read-only and PAGE_DIRTY_HW PTE > > setting is reserved only for the Shadow Stack.  To track dirty of > > non-Shadow Stack read-only PTEs, we use PAGE_DIRTY_SW. > > > > Update ptep_set_wrprotect() and pmdp_set_wrprotect(). > > > > Signed-off-by: Yu-cheng Yu > > --- > >  arch/x86/include/asm/pgtable.h | 42 > > ++++++++++++++++++++++++++++++++++ > >  1 file changed, 42 insertions(+) > > > > diff --git a/arch/x86/include/asm/pgtable.h > > b/arch/x86/include/asm/pgtable.h > > index 4d50de77ea96..556ef258eeff 100644 > > --- a/arch/x86/include/asm/pgtable.h > > +++ b/arch/x86/include/asm/pgtable.h > > @@ -1203,7 +1203,28 @@ static inline pte_t > > ptep_get_and_clear_full(struct mm_struct *mm, > >  static inline void ptep_set_wrprotect(struct mm_struct *mm, > >         unsigned long addr, pte_t > > *ptep) > >  { > > + pte_t pte; > > + > >   clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte); > > + pte = *ptep; > > + > > + /* > > +  * Some processors can start a write, but ending up > > seeing >                                       but end up seeing > > > > > +  * a read-only PTE by the time they get to the Dirty bit. > > +  * In this case, they will set the Dirty bit, leaving a > > +  * read-only, Dirty PTE which looks like a Shadow Stack > > PTE. > > +  * > > +  * However, this behavior has been improved and will not > > occur > > +  * on processors supporting Shadow Stacks.  Without this > > +  * guarantee, a transition to a non-present PTE and flush > > the > > +  * TLB would be needed. > > +  * > > +  * When change a writable PTE to read-only and if the PTE > > has >         changing > > > > > +  * _PAGE_DIRTY_HW set, we move that bit to _PAGE_DIRTY_SW > > so > > +  * that the PTE is not a valid Shadow Stack PTE. > > +  */ > > + pte = pte_move_flags(pte, _PAGE_DIRTY_HW, > > _PAGE_DIRTY_SW); > > + set_pte_at(mm, addr, ptep, pte); > >  } > >   > >  #define flush_tlb_fix_spurious_fault(vma, address) do { } while > > (0) > > @@ -1266,7 +1287,28 @@ static inline pud_t > > pudp_huge_get_and_clear(struct mm_struct *mm, > >  static inline void pmdp_set_wrprotect(struct mm_struct *mm, > >         unsigned long addr, pmd_t > > *pmdp) > >  { > > + pmd_t pmd; > > + > >   clear_bit(_PAGE_BIT_RW, (unsigned long *)pmdp); > > + pmd = *pmdp; > > + > > + /* > > +  * Some processors can start a write, but ending up > > seeing >                                       but end up seeing > > > > > +  * a read-only PTE by the time they get to the Dirty bit. > > +  * In this case, they will set the Dirty bit, leaving a > > +  * read-only, Dirty PTE which looks like a Shadow Stack > > PTE. > > +  * > > +  * However, this behavior has been improved and will not > > occur > > +  * on processors supporting Shadow Stacks.  Without this > > +  * guarantee, a transition to a non-present PTE and flush > > the > > +  * TLB would be needed. > > +  * > > +  * When change a writable PTE to read-only and if the PTE > > has >         changing > > > > > +  * _PAGE_DIRTY_HW set, we move that bit to _PAGE_DIRTY_SW > > so > > +  * that the PTE is not a valid Shadow Stack PTE. > > +  */ > > + pmd = pmd_move_flags(pmd, _PAGE_DIRTY_HW, > > _PAGE_DIRTY_SW); > > + set_pmd_at(mm, addr, pmdp, pmd); > >  } > >   > >  #define pud_write pud_write > > > Thanks, I will fix it!