From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-5.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id 19C697D90D for ; Tue, 27 Aug 2019 15:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730237AbfH0PI5 (ORCPT ); Tue, 27 Aug 2019 11:08:57 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:58790 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729471AbfH0PI5 (ORCPT ); Tue, 27 Aug 2019 11:08:57 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x7RF27Pt026516; Tue, 27 Aug 2019 17:08:29 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=STMicroelectronics; bh=TSHHKZbTbPEz3I4WS/hkuIsYqvLXHvNxoNE+mdsAexQ=; b=nzwnm4kYp74KljkEYhZcfPzGsxTUmScuxOOTuaZA3SPmwYQwLJ0FJusAFhNYOHGAx/Lt aT5JRrM0UUw8gPUYhLiUhtz88WMkv0obE7MU2f152l1KI87+KnNyjgRgzxqII/baast9 jHOxQab0YymERK26UGBkIrYskfz/l1QJt4UaZTvkCkZlIw+dBa5U6hEK6xFR9EJuBSeu +1zukOzq6bnKw28/MxbADQoc+SfYdgqlROQiJw2AUUi5YZ+hQpWq6JZKQQEvT55Sjshe m/jJ86+fvFumBQdz8zI2paBjpU3ryHoQ2wCUjYGF9L4m8GZtE0aXCTdWkFBteHwEScgz sQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx08-00178001.pphosted.com with ESMTP id 2ujv4kt4ar-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 27 Aug 2019 17:08:29 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7ABB051; Tue, 27 Aug 2019 15:08:20 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D88CC2B8A04; Tue, 27 Aug 2019 17:08:19 +0200 (CEST) Received: from SFHDAG5NODE1.st.com (10.75.127.13) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 27 Aug 2019 17:08:19 +0200 Received: from SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6]) by SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6%20]) with mapi id 15.00.1473.003; Tue, 27 Aug 2019 17:08:19 +0200 From: Gerald BAEZA To: "will@kernel.org" , "mark.rutland@arm.com" , "robh+dt@kernel.org" , "mcoquelin.stm32@gmail.com" , Alexandre TORGUE , "corbet@lwn.net" , "linux@armlinux.org.uk" , "olof@lixom.net" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-kernel@vger.kernel.org" , "linux-doc@vger.kernel.org" CC: Gerald BAEZA Subject: [PATCH v3 1/5] Documentation: perf: stm32: ddrperfm support Thread-Topic: [PATCH v3 1/5] Documentation: perf: stm32: ddrperfm support Thread-Index: AQHVXOlCuooLJYba9EevlKK6UKzhyQ== Date: Tue, 27 Aug 2019 15:08:19 +0000 Message-ID: <1566918464-23927-2-git-send-email-gerald.baeza@st.com> References: <1566918464-23927-1-git-send-email-gerald.baeza@st.com> In-Reply-To: <1566918464-23927-1-git-send-email-gerald.baeza@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-08-27_03:,, signatures=0 Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC. This documentation introduces the DDRPERFM, the stm32-ddr-pmu driver supporting it and how to use it with the perf tool. Signed-off-by: Gerald Baeza --- Documentation/perf/stm32-ddr-pmu.txt | 37 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/perf/stm32-ddr-pmu.txt diff --git a/Documentation/perf/stm32-ddr-pmu.txt b/Documentation/perf/stm3= 2-ddr-pmu.txt new file mode 100644 index 0000000..557bf47 --- /dev/null +++ b/Documentation/perf/stm32-ddr-pmu.txt @@ -0,0 +1,37 @@ +STM32 DDR Performance Monitor (DDRPERFM) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC. +See Documentation/arm/stm32/stm32mp157-overview.rst to get access to +STM32MP157 reference manual RM0436 where DDRPERFM is described. + + +The five following counters are supported by stm32-ddr-pmu driver: + cnt0: read operations counters (read_cnt) + cnt1: write operations counters (write_cnt) + cnt2: active state counters (activate_cnt) + cnt3: idle state counters (idle_cnt) + tcnt: time count, present for all sets (time_cnt) + +The stm32-ddr-pmu driver relies on the perf PMU framework to expose the +counters via sysfs: + $ ls /sys/bus/event_source/devices/ddrperfm/events + activate_cnt idle_cnt read_cnt time_cnt write_cnt + + +The perf PMU framework is usually invoked via the 'perf stat' tool. + +The DDRPERFM is a system monitor that cannot isolate the traffic coming fr= om a +given thread or CPU, that is why stm32-ddr-pmu driver rejects any 'perf st= at' +call that does not request a system-wide collection: the '-a, --all-cpus' +option is mandatory! + +Example: + $ perf stat -e ddrperfm/read_cnt/,ddrperfm/time_cnt/ -a sleep 20 + Performance counter stats for 'system wide': + + 342541560 ddrperfm/read_cnt/ + 10660011400 ddrperfm/time_cnt/ + + 20.021068551 seconds time elapsed + --=20 2.7.4