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From: Babu Moger <babu.moger@amd.com>
To: <corbet@lwn.net>, <reinette.chatre@intel.com>,
	<tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>
Cc: <fenghua.yu@intel.com>, <dave.hansen@linux.intel.com>,
	<x86@kernel.org>, <hpa@zytor.com>, <paulmck@kernel.org>,
	<akpm@linux-foundation.org>, <quic_neeraju@quicinc.com>,
	<rdunlap@infradead.org>, <damien.lemoal@opensource.wdc.com>,
	<songmuchun@bytedance.com>, <peterz@infradead.org>,
	<jpoimboe@kernel.org>, <pbonzini@redhat.com>,
	<babu.moger@amd.com>, <chang.seok.bae@intel.com>,
	<pawan.kumar.gupta@linux.intel.com>, <jmattson@google.com>,
	<daniel.sneddon@linux.intel.com>, <sandipan.das@amd.com>,
	<tony.luck@intel.com>, <james.morse@arm.com>,
	<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<bagasdotme@gmail.com>, <eranian@google.com>
Subject: [PATCH v5 09/12] x86/resctrl: Add sysfs interface to write mbm_total_bytes event configuration
Date: Tue, 27 Sep 2022 15:26:39 -0500	[thread overview]
Message-ID: <166431039972.373387.17483031820875867626.stgit@bmoger-ubuntu> (raw)
In-Reply-To: <166431016617.373387.1968875281081252467.stgit@bmoger-ubuntu>

The current event configuration can be changed by the user by writing
to the configuration file /sys/fs/resctrl/info/L3_MON/mbm_total_config.
The event configuration settings are domain specific. Changing the
configuration on one CPU in a domain would affect the whole domain.

Following are the types of events supported:

====  ===========================================================
Bits   Description
====  ===========================================================
6      Dirty Victims from the QOS domain to all types of memory
5      Reads to slow memory in the non-local NUMA domain
4      Reads to slow memory in the local NUMA domain
3      Non-temporal writes to non-local NUMA domain
2      Non-temporal writes to local NUMA domain
1      Reads to memory in the non-local NUMA domain
0      Reads to memory in the local NUMA domain
====  ===========================================================

For example:
To change the mbm_total_bytes to count all the reads on domain 0, run
the command.
	$echo  0:0x33 > /sys/fs/resctrl/info/L3_MON/mbm_total_config

To change the mbm_total_bytes to count all the slow memory reads on
domain 1, run the command.
	$echo  1:0x30 > /sys/fs/resctrl/info/L3_MON/mbm_total_config

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 arch/x86/kernel/cpu/resctrl/internal.h |   23 +++++
 arch/x86/kernel/cpu/resctrl/rdtgroup.c |  139 ++++++++++++++++++++++++++++++++
 2 files changed, 162 insertions(+)

diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 44d3f18dfd69..d19ade3b5ef3 100644
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -51,6 +51,29 @@
  */
 #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE)
 
+/* Reads to Local DRAM Memory */
+#define READS_TO_LOCAL_MEM             BIT(0)
+
+/* Reads to Remote DRAM Memory */
+#define READS_TO_REMOTE_MEM            BIT(1)
+
+/* Non-Temporal Writes to Local Memory */
+#define NON_TEMP_WRITE_TO_LOCAL_MEM    BIT(2)
+
+/* Non-Temporal Writes to Remote Memory */
+#define NON_TEMP_WRITE_TO_REMOTE_MEM   BIT(3)
+
+/* Reads to Local Memory the system identifies as "Slow Memory" */
+#define READS_TO_LOCAL_S_MEM           BIT(4)
+
+/* Reads to Remote Memory the system identifies as "Slow Memory" */
+#define READS_TO_REMOTE_S_MEM          BIT(5)
+
+/* Dirty Victims to All Types of Memory */
+#define  DIRTY_VICTIMS_TO_ALL_MEM      BIT(6)
+
+/* Max event bits supported */
+#define MAX_EVT_CONFIG_BITS            GENMASK(6, 0)
 
 struct rdt_fs_context {
 	struct kernfs_fs_context	kfc;
diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index 27bf6ade0dbf..c1d43d03846a 100644
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -1491,6 +1491,144 @@ static int mbm_local_config_show(struct kernfs_open_file *of,
 	return 0;
 }
 
+void mon_event_config_write(void *info)
+{
+	struct mon_config_info *mon_info = info;
+	u32 msr_index;
+
+	switch (mon_info->evtid) {
+	case QOS_L3_MBM_TOTAL_EVENT_ID:
+		msr_index = 0;
+		break;
+	case QOS_L3_MBM_LOCAL_EVENT_ID:
+		msr_index = 1;
+		break;
+	default:
+		/* Not expected to come here */
+		return;
+	}
+
+	wrmsr(MSR_IA32_EVT_CFG_BASE + msr_index, mon_info->mon_config, 0);
+}
+
+int mbm_config_write(struct rdt_resource *r, struct rdt_domain *d,
+		     u32 evtid, u32 val)
+{
+	struct mon_config_info mon_info = {0};
+	cpumask_var_t cpu_mask;
+	int ret = 0, cpu;
+
+	rdt_last_cmd_clear();
+
+	/* mon_config cannot be more than the supported set of events */
+	if (val > MAX_EVT_CONFIG_BITS) {
+		rdt_last_cmd_puts("Invalid event configuration\n");
+		return -EINVAL;
+	}
+
+	cpus_read_lock();
+
+	if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) {
+		rdt_last_cmd_puts("cpu_mask allocation failed\n");
+		ret = -ENOMEM;
+		goto e_unlock;
+	}
+
+	/*
+	 * Read the current config value first. If both are same then
+	 * we dont need to write it again.
+	 */
+	mon_info.evtid = evtid;
+	mondata_config_read(d, &mon_info);
+	if (mon_info.mon_config == val)
+		goto e_cpumask;
+
+	mon_info.mon_config = val;
+
+	/* Pick all the CPUs in the domain instance */
+	for_each_cpu(cpu, &d->cpu_mask)
+		cpumask_set_cpu(cpu, cpu_mask);
+
+	/* Update MSR_IA32_EVT_CFG_BASE MSR on all the CPUs in cpu_mask */
+	on_each_cpu_mask(cpu_mask, mon_event_config_write, &mon_info, 1);
+
+	/*
+	 * When an Event Configuration is changed, the bandwidth counters
+	 * for all RMIDs and Events will be cleared by the hardware. The
+	 * hardware also sets MSR_IA32_QM_CTR.Unavailable (bit 62) for
+	 * every RMID on the next read to any event for every RMID.
+	 * Subsequent reads will have MSR_IA32_QM_CTR.Unavailable (bit 62)
+	 * cleared while it is tracked by the hardware. Clear the
+	 * mbm_local and mbm_total counts for all the RMIDs.
+	 */
+	memset(d->mbm_local, 0, sizeof(struct mbm_state) * r->num_rmid);
+	memset(d->mbm_total, 0, sizeof(struct mbm_state) * r->num_rmid);
+
+e_cpumask:
+	free_cpumask_var(cpu_mask);
+
+e_unlock:
+	cpus_read_unlock();
+
+	return ret;
+}
+
+unsigned int mon_config_parse(struct rdt_resource *r, char *tok, u32 evtid)
+{
+	char *dom_str = NULL, *id_str;
+	struct rdt_domain *d;
+	unsigned long dom_id, val;
+	int ret = 0;
+
+next:
+	if (!tok || tok[0] == '\0')
+		return 0;
+
+	/* Start processing the strings for each domain */
+	dom_str = strim(strsep(&tok, ";"));
+	id_str = strsep(&dom_str, "=");
+
+	if (!dom_str || kstrtoul(id_str, 10, &dom_id)) {
+		rdt_last_cmd_puts("Missing '=' or non-numeric domain id\n");
+		return -EINVAL;
+	}
+
+	if (!dom_str || kstrtoul(dom_str, 16, &val)) {
+		rdt_last_cmd_puts("Missing '=' or non-numeric event configuration value\n");
+		return -EINVAL;
+	}
+
+	list_for_each_entry(d, &r->domains, list) {
+		if (d->id == dom_id) {
+			ret = mbm_config_write(r, d, evtid, val);
+			if (ret)
+				return -EINVAL;
+			goto next;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static ssize_t mbm_total_config_write(struct kernfs_open_file *of,
+				      char *buf, size_t nbytes, loff_t off)
+{
+	struct rdt_resource *r = of->kn->parent->priv;
+	int ret;
+
+	/* Valid input requires a trailing newline */
+	if (nbytes == 0 || buf[nbytes - 1] != '\n')
+		return -EINVAL;
+
+	rdt_last_cmd_clear();
+
+	buf[nbytes - 1] = '\0';
+
+	ret = mon_config_parse(r, buf, QOS_L3_MBM_TOTAL_EVENT_ID);
+
+	return ret ?: nbytes;
+}
+
 /* rdtgroup information files for one cache resource. */
 static struct rftype res_common_files[] = {
 	{
@@ -1594,6 +1732,7 @@ static struct rftype res_common_files[] = {
 		.mode		= 0644,
 		.kf_ops		= &rdtgroup_kf_single_ops,
 		.seq_show	= mbm_total_config_show,
+		.write		= mbm_total_config_write,
 	},
 	{
 		.name		= "mbm_local_config",



  parent reply	other threads:[~2022-09-27 20:27 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-27 20:25 [PATCH v5 00/12] x86/resctrl: Support for AMD QoS new features Babu Moger
2022-09-27 20:25 ` [PATCH v5 01/12] x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag Babu Moger
2022-09-29 21:58   ` Reinette Chatre
2022-10-03 14:45     ` Moger, Babu
2022-10-03 15:24       ` Reinette Chatre
2022-10-03 15:35         ` Moger, Babu
2022-09-27 20:25 ` [PATCH v5 02/12] x86/resctrl: Add a new resource type RDT_RESOURCE_SMBA Babu Moger
2022-09-27 20:25 ` [PATCH v5 03/12] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag Babu Moger
2022-09-27 20:25 ` [PATCH v5 04/12] x86/resctrl: Include new features in command line options Babu Moger
2022-09-27 20:26 ` [PATCH v5 05/12] x86/resctrl: Detect and configure Slow Memory Bandwidth allocation Babu Moger
2022-09-27 20:26 ` [PATCH v5 06/12] x86/resctrl: Introduce data structure to support monitor configuration Babu Moger
2022-09-27 22:25   ` Yu, Fenghua
2022-09-28 12:56     ` Moger, Babu
2022-09-27 20:26 ` [PATCH v5 07/12] x86/resctrl: Add sysfs interface to read mbm_total_bytes event configuration Babu Moger
2022-09-27 20:26 ` [PATCH v5 08/12] x86/resctrl: Add sysfs interface to read mbm_local_bytes " Babu Moger
2022-09-27 22:42   ` Yu, Fenghua
2022-09-28 14:43     ` Moger, Babu
2022-09-27 20:26 ` Babu Moger [this message]
2022-09-27 22:32   ` [PATCH v5 09/12] x86/resctrl: Add sysfs interface to write mbm_total_bytes " Yu, Fenghua
2022-09-28 12:58     ` Moger, Babu
2022-09-27 20:26 ` [PATCH v5 10/12] x86/resctrl: Add sysfs interface to write mbm_local_bytes " Babu Moger
2022-09-27 20:26 ` [PATCH v5 11/12] x86/resctrl: Replace smp_call_function_many() with on_each_cpu_mask() Babu Moger
2022-09-27 20:27 ` [PATCH v5 12/12] Documentation/x86: Update resctrl_ui.rst for new features Babu Moger
2022-09-28  4:25   ` Bagas Sanjaya
2022-09-28 15:23     ` Moger, Babu
2022-09-29  8:48       ` Bagas Sanjaya
2022-09-29 13:22         ` Moger, Babu
2022-09-29 13:33           ` Bagas Sanjaya
2022-09-29 22:10   ` Reinette Chatre
2022-10-03 14:28     ` Moger, Babu
2022-10-03 15:36       ` Reinette Chatre
2022-10-04 14:00         ` Moger, Babu
2022-10-04 16:15           ` Reinette Chatre
     [not found]             ` <a7766c60-5e2e-77f7-97ba-8a9628d3cca8@amd.com>
2022-10-04 19:05               ` Reinette Chatre
2022-10-07  8:33 ` [PATCH v5 00/12] x86/resctrl: Support for AMD QoS " Bagas Sanjaya
2022-10-07 15:51   ` Moger, Babu

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