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Tue, 6 May 2025 04:27:16 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Jiri Pirko , Gal Pressman , "Leon Romanovsky" , Donald Hunter , "Jiri Pirko" , Jonathan Corbet , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , , , , , Moshe Shemesh , Mark Bloch , Carolina Jubran , Cosmin Ratiu Subject: [PATCH net-next V8 2/5] net/mlx5: Add no-op implementation for setting tc-bw on rate objects Date: Tue, 6 May 2025 14:26:40 +0300 Message-ID: <1746530803-450152-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1746530803-450152-1-git-send-email-tariqt@nvidia.com> References: <1746530803-450152-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|PH7PR12MB8037:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a2c94ab-3e1b-43c5-404a-08dd8c90fd75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?K9SlgPC4zk66SX7E1D6oKTAeSwMLiQfYWRTgJrPXRCPy5Jx+LDh09XnnSXx7?= =?us-ascii?Q?jHomPzzFSEabDcqBEvxeq64pFz7ZQz4ZFhyzvdHarJdmg/2mK7XLKOJLT5Nm?= =?us-ascii?Q?3UJ2C+XIZdp2E32dsgJASmIvQ/Pb7BcplHCbUNpT6yFj+X6cWzgJcRNBR7Of?= =?us-ascii?Q?TKgMkeCwEfAKyKyVsf3zS/x8t2wC8st6caK7dOEq73UMaH9x8VXKDX4L+F5T?= =?us-ascii?Q?buHvTMR6Q7wp5wMZ/CmXD8J1TwDi3M0ILAR2vG2BZGmN9Rh3n04RPGZ0sdmU?= =?us-ascii?Q?WSCWn9qbK6qKYHgRB/oDASjELTStDbqCBeVSv6LV7EVciifSO04APqxYQSKr?= =?us-ascii?Q?Gp1zQlkRF66oliKYOGr7N1DgyELkTiN2c9ldyGBXZE4N2odZ0kmjpQTkFjaW?= =?us-ascii?Q?fMaG1TQyFtd8VIZuibXIxdMfypUJ53fjZbZ0NpniueUIRYjqvTT3QE7NDEMQ?= =?us-ascii?Q?bL6ByR28MhkoQwL5WvvhyYOrMNkrg7muYJjTNobgf3D75Jr0q6k5loYAvclg?= =?us-ascii?Q?7JGqELwhQEXSJt/ToK8CwZgqjR5EKv3YzF7phQf43tJe+k+DYeceiYYzLAuY?= =?us-ascii?Q?n0FigNlBx+MHe2u/sGSW7HrebW+HXkNdQrg/FpjHQ96MHT0eegHDoc96uDkB?= =?us-ascii?Q?5P26CT8xuwY/hQaugRWYmt58YCQ+EFxbbYBfCryD6GEreo1b7l6pg1IDO+JA?= =?us-ascii?Q?i10PLsPQYl5Jbfs/fL5+UJKksjRkLC81Ul1fKWPbF3vZozg33ZgypVm7iOy8?= =?us-ascii?Q?d/uAygn5tSLJW//58LbI0P952hXoDkYQMvfeTlKWPXFYPWC0VxEK+wi61aSM?= =?us-ascii?Q?LUsFj+9lpFJlxHyEOks0DlwNwZmJarNujegJwEkr2CU5Rr00wzqb1XYlQeHt?= =?us-ascii?Q?vR19KM+XaA9YEnOQa4PgnFd++T1a9Czsy9GyzJn8AOPNUauM5CGzEOYkwJpB?= =?us-ascii?Q?sgxUWFvHK0eu/0rPM7K2ImYHLqphdIoD0VvvotCVibqaM9LbS9RpSDx6AGNw?= =?us-ascii?Q?6nV78s3waMTIbw26Sfwk4bWpIVLPeS7LXUAscY+bakSJylh3YRL+vIdctAQL?= =?us-ascii?Q?zYJ1iNb/Aop7J1++b6IxRdWb00NfqO8MzLnRQx4H2tBOwuTJS7TlA+7Hcmbq?= =?us-ascii?Q?PhLjB1267mcxkFeodF70rtiECrBtEvSS15eAo+1V2ujbQkkW+dlGgRw0ryrW?= =?us-ascii?Q?UX67HrInvN89rE3vl+vUz7DwsIizzjuYToAa3tTr0ahSIZO367bQRHy7UinN?= =?us-ascii?Q?r5+YmaBStezLWovkEmt3MupV8R7kPu8dziVOQIHx0/RjEpgp3WeX1Lgbzn/t?= =?us-ascii?Q?sM029oJdvTNhkNF3iqCRawVqE85GAkjV89VlalA++khInoM/wgOEbFNle337?= =?us-ascii?Q?+oyheIhfOHL0bqCNADpk/5MvHy26pIQcznU0qP4ap3WFT+T0AOlG7KWPx8Zs?= =?us-ascii?Q?zRuUmE7J95+xfe3C20CXJL+EIIqcHF1Sz4NIkb/nWK9IVez6Xl6MV1yX++bj?= =?us-ascii?Q?U55j9RdT//cnbnsaQ7ejw67IVKUSw5tvceJn?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2025 11:27:31.1705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a2c94ab-3e1b-43c5-404a-08dd8c90fd75 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8037 From: Carolina Jubran Introduce `mlx5_esw_devlink_rate_node_tc_bw_set()` and `mlx5_esw_devlink_rate_leaf_tc_bw_set()` with no-op logic. Future patches will add support for setting traffic class bandwidth on rate objects. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/devlink.c | 2 ++ .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 20 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/esw/qos.h | 8 ++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c index 73cd74644378..47d3acd011cf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -323,6 +323,8 @@ static const struct devlink_ops mlx5_devlink_ops = { .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, .rate_leaf_tx_share_set = mlx5_esw_devlink_rate_leaf_tx_share_set, .rate_leaf_tx_max_set = mlx5_esw_devlink_rate_leaf_tx_max_set, + .rate_leaf_tc_bw_set = mlx5_esw_devlink_rate_leaf_tc_bw_set, + .rate_node_tc_bw_set = mlx5_esw_devlink_rate_node_tc_bw_set, .rate_node_tx_share_set = mlx5_esw_devlink_rate_node_tx_share_set, .rate_node_tx_max_set = mlx5_esw_devlink_rate_node_tx_max_set, .rate_node_new = mlx5_esw_devlink_rate_node_new, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index b6ae384396b3..ec706e9352e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -906,6 +906,26 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void * return err; } +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_leaf, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, + "TC bandwidth shares are not supported on leafs"); + return -EOPNOTSUPP; +} + +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, + "TC bandwidth shares are not supported on nodes"); + return -EOPNOTSUPP; +} + int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, u64 tx_share, struct netlink_ext_ack *extack) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h index ed40ec8f027e..0a50982b0e27 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h @@ -21,6 +21,14 @@ int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf, void u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void *priv, u64 tx_max, struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, + void *priv, + u32 *tc_bw, + struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void *priv, -- 2.31.1