Re: [PATCH v4 03/10] riscv: hwprobe: Export Zalasr extension

Guo Ren
2025-10-20T13:47:06Z

On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> Export the Zalasr extension to userspace using hwprobe.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 5 ++++-
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 2aa9be272d5de..067a3595fb9d5 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -249,6 +249,9 @@ The following keys are defined:
> defined in the in the RISC-V ISA manual starting from commit e87412e621f1
> ("integrate Zaamo and Zalrsc text (#1304)").
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
> + frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
"Frozen Version 0.9" might not be proper; it denotes the current
temporary state, not the goal of the patch.

> +
> * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
> defined in the in the RISC-V ISA manual starting from commit e87412e621f1
> ("integrate Zaamo and Zalrsc text (#1304)").
> @@ -360,4 +363,4 @@ The following keys are defined:
>
> * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
> vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
> - Instruction Extensions Specification.
> \ No newline at end of file
> + Instruction Extensions Specification.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index aaf6ad9704993..d3a65f8ff7da4 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -82,6 +82,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
> #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
> #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
> +#define RISCV_HWPROBE_EXT_ZALASR (1ULL << 59)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 0b170e18a2beb..0529e692b1173 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -99,6 +99,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZAAMO);
> EXT_KEY(ZABHA);
> EXT_KEY(ZACAS);
> + EXT_KEY(ZALASR);
> EXT_KEY(ZALRSC);
> EXT_KEY(ZAWRS);
> EXT_KEY(ZBA);
> --
> 2.20.1
>

--
Best Regards
Guo Ren