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De Francesco" To: Dave Jiang , Gregory Price Cc: linux-cxl@vger.kernel.org, Davidlohr Bueso , Jonathan Cameron , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] cxl: docs/driver-api/conventions resolve conflicts btw CFMWS, LMH, ED Date: Fri, 04 Jul 2025 12:05:33 +0200 Message-ID: <1985851.b9uPGUboIS@fdefranc-mobl3> In-Reply-To: References: <20250623152923.1048525-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Thursday, July 3, 2025 9:40:21=E2=80=AFPM Central European Summer Time G= regory Price wrote: > On Tue, Jul 01, 2025 at 08:23:57AM -0700, Dave Jiang wrote: > >=20 > >=20 > > On 6/23/25 12:19 PM, Gregory Price wrote: > > > On Mon, Jun 23, 2025 at 05:29:02PM +0200, Fabio M. De Francesco wrote: > > >> Add documentation on how to resolve conflicts between CXL Fixed Memo= ry > > >> Windows, Platform Memory Holes, and Endpoint Decoders. > > >> > > >> Signed-off-by: Fabio M. De Francesco > > >=20 > > > I won't block a doc update on a suggestion so > > >=20 > > > Reviewed-by: Gregory Price > > >=20 > > >> +Platform Firmware (BIOS) might reserve part of physical addresses b= elow > > >> +4 GB (e.g., the Low Memory Hole that describes PCIe memory space fo= r MMIO > > >> +or a requirement for the greater than 8 way interleave CXL regions = starting > > >> +at address 0). In that case the Window Size value cannot be anymore > > >> +constrained to the NIW * 256 MB above-mentioned rule. > > >=20 > > > It might be nice to have a diagram that explains this visually, as it= 's > > > difficult for me to understand the implications through words alone... > >=20 > > +1 on request for diagram to explain. We should try to document this is= sue as clearly as possible. Thank you. > > >=20 > At the very least, it would be nice to have an explicitly example that > explains the expected cfmws/decoder configurations that are valid but > "technically" violate the spec >=20 > I *think* this basically boils down to "CFMWS size is not aligned, but > all the decoders it targets are"? If I understand this correctly? >=20 Yes, this is the intended meaning.=20 E.g, two windows, 384 GB total memory, LMH at 2 GB: Window | CFMWS Base | CFMWS Size | HDM Decoder Base | HDM Decoder Size | Wa= ys | Granularity 0 | 0 GB | 2 GB | 0 GB | 3 GB | 1= 2 | 256 1 | 4 GB | 380 GB | 0 GB | 380 GB | 1= 2 | 256 12 *256MB =3D 3GB, the Top of Low memory below 4GB is set as 2GB in the pla= tform for MMIO Low Mem Hole (2-4GB). Only 2GB will be potentially available= for user, but currently the CXL driver expects a CFMWS range's size to be = greater or equal to the HDM Decoder's, so it doesn't match them and we los= e those 2GB described by CFMWS0. If we allow the matching, we make those 2G= B available to users. Is a table like the one above good enough to make this subject clearer? Thanks, =46abio > > > >=20 > > > which is likely why the conflict exists in the first place :] > > >=20 > > > ~Gregory > >=20 >=20