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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2025 15:35:11.7159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43da8b63-f640-403e-2433-08ddf5ffca6c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4190 Hi Naveen, Thank you for reviewing my patches. On 9/8/2025 7:09 PM, Naveen N Rao wrote: > On Mon, Sep 01, 2025 at 10:52:12AM +0530, Manali Shukla wrote: >> From: Santosh Shukla >> >> Local interrupts can be extended to include more LVT registers in >> order to allow additional interrupt sources, like Instruction Based >> Sampling (IBS). >> >> The Extended APIC feature register indicates the number of extended >> Local Vector Table(LVT) registers in the local APIC. Currently, there >> are 4 extended LVT registers available which are located at APIC >> offsets (400h-530h). >> >> The EXTLVT feature bit changes the behavior associated with reading >> and writing an extended LVT register when AVIC is enabled. When the >> EXTLVT and AVIC are enabled, a write to an extended LVT register >> changes from a fault style #VMEXIT to a trap style #VMEXIT and a read >> of an extended LVT register no longer triggers a #VMEXIT [2]. >> >> Presence of the EXTLVT feature is indicated via CPUID function >> 0x8000000A_EDX[27]. >> >> More details about the EXTLVT feature can be found at [1]. >> >> [1]: AMD Programmer's Manual Volume 2, >> Section 16.4.5 Extended Interrupts. >> https://bugzilla.kernel.org/attachment.cgi?id=306250 >> >> [2]: AMD Programmer's Manual Volume 2, >> Table 15-22. Guest vAPIC Register Access Behavior. >> https://bugzilla.kernel.org/attachment.cgi?id=306250 >> >> Signed-off-by: Santosh Shukla >> Signed-off-by: Manali Shukla >> --- >> arch/x86/include/asm/cpufeatures.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >> index 286d509f9363..0dd44cbf7196 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -378,6 +378,7 @@ >> #define X86_FEATURE_X2AVIC (15*32+18) /* "x2avic" Virtual x2apic */ >> #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */ >> #define X86_FEATURE_VNMI (15*32+25) /* "vnmi" Virtual NMI */ >> +#define X86_FEATURE_EXTLVT (15*32+27) /* Extended Local vector Table */ > > Per APM Vol 3, Appendix E.4.9 "Function 8000_000Ah", bit 27 is: > ExtLvtAvicAccessChgExtended: Interrupt Local Vector Table Register AVIC > Access changes. See “Virtual APIC Register Accesses.” > > And, APM Vol 2, 15.29.3.1 "Virtual APIC Register Accesses" says: > Extended Interrupt [3:0] Local Vector Table Registers: > CPUID Fn8000_000A_EDX[27]=1: > Read: Allowed > Write: #VMEXIT (trap) > CPUID Fn8000_000A_EDX[27]=0: > Read: #VMEXIT (fault) > Write: #VMEXIT(fault) > > So, as far as I can tell, this feature is only used to determine how > AVIC hardware handles accesses to the extended LVT entries. Does this > matter for vIBS? In the absence of this feature, we should take a fault > and KVM should be able to handle that. > Yes, but KVM still needs to emulate extended LVT registers to handle the fault when the guest IBS driver attempts to read/write extended LVT registers. "KVM: x86: Add emulation support for Extented LVT registers" patch covers two aspects: Extended LVT register emulation (EXTAPIC feature bit in CPUID 0x80000001:ECX[3]) ExtLvtAvicAccessChgExtended which changes the behavior of read/write access when AVIC is enabled. > > - Naveen >