From: Pierre Gondois <pierre.gondois@arm.com>
To: Sumit Gupta <sumitg@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
acpica-devel@lists.linux.dev, linux-doc@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org,
zhanjie9@hisilicon.com, ionela.voinescu@arm.com,
perry.yuan@amd.com, mario.limonciello@amd.com,
gautham.shenoy@amd.com, ray.huang@amd.com, rdunlap@infradead.org,
zhenglifeng1@huawei.com, corbet@lwn.net, robert.moore@intel.com,
lenb@kernel.org, viresh.kumar@linaro.org, rafael@kernel.org,
treding@nvidia.com, jonathanh@nvidia.com, vsethi@nvidia.com,
ksitaraman@nvidia.com, sanjayc@nvidia.com, nhartman@nvidia.com,
bbasu@nvidia.com
Subject: Re: [PATCH v4 5/8] ACPI: CPPC: add APIs and sysfs interface for perf_limited register
Date: Thu, 27 Nov 2025 15:54:12 +0100 [thread overview]
Message-ID: <1decddd7-54d7-4e7e-922d-b68b901bf9aa@arm.com> (raw)
In-Reply-To: <20251105113844.4086250-6-sumitg@nvidia.com>
On 11/5/25 12:38, Sumit Gupta wrote:
> Add sysfs interface to read/write the Performance Limited register.
>
> The Performance Limited register indicates to the OS that an
> unpredictable event (like thermal throttling) has limited processor
> performance. This register is sticky and remains set until reset or
> OS clears it by writing 0.
>
> The interface is exposed as:
> /sys/devices/system/cpu/cpuX/cpufreq/perf_limited
>
> Signed-off-by: Sumit Gupta<sumitg@nvidia.com>
> ---
> drivers/acpi/cppc_acpi.c | 26 ++++++++++++++++++++++++++
> drivers/cpufreq/cppc_cpufreq.c | 12 ++++++++++++
> include/acpi/cppc_acpi.h | 10 ++++++++++
> 3 files changed, 48 insertions(+)
>
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index ef53eb8a1feb..9b8da3ef06db 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -1810,6 +1810,32 @@ int cppc_set_max_perf(int cpu, u64 max_perf)
> }
> EXPORT_SYMBOL_GPL(cppc_set_max_perf);
>
> +/**
> + * cppc_get_perf_limited - Get the Performance Limited register value.
> + * @cpu: CPU from which to get Performance Limited register.
> + * @perf_limited: Pointer to store the Performance Limited value.
> + *
> + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if not supported.
> + */
> +int cppc_get_perf_limited(int cpu, u64 *perf_limited)
> +{
> + return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited);
> +}
> +EXPORT_SYMBOL_GPL(cppc_get_perf_limited);
> +
> +/**
> + * cppc_set_perf_limited() - Write the Performance Limited register.
> + * @cpu: CPU on which to write register.
> + * @perf_limited: Value to write to the perf_limited register.
> + *
> + * Return: 0 for success, -EIO on register access failure, -EOPNOTSUPP if not supported.
> + */
> +int cppc_set_perf_limited(int cpu, u64 perf_limited)
> +{
> + return cppc_set_reg_val(cpu, PERF_LIMITED, perf_limited);
> +}
There are currently only 2 bits used:
- 0 Desired_Excursion
- 1 Minimum_Excursion
It might be worth defining these bits and mask the values when trying to
set the register.
------
Also NIT:
The spec. says:
" All accesses to the Performance Limited Register must be made using
interlocked operations, by both accessing entities."
I am not sure I understand which synchronization issues are faced.
It's just to report the comment from the spec.
> +EXPORT_SYMBOL_GPL(cppc_set_perf_limited);
> +
> /**
> * cppc_get_perf - Get a CPU's performance controls.
> * @cpu: CPU for which to get performance controls.
> diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c
> index cde6202e9c51..a425ad575aa6 100644
> --- a/drivers/cpufreq/cppc_cpufreq.c
> +++ b/drivers/cpufreq/cppc_cpufreq.c
> @@ -1043,12 +1043,23 @@ static ssize_t store_max_perf(struct cpufreq_policy *policy, const char *buf, si
> return count;
> }
>
> +static ssize_t show_perf_limited(struct cpufreq_policy *policy, char *buf)
> +{
> + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_perf_limited, buf);
> +}
> +
> +static ssize_t store_perf_limited(struct cpufreq_policy *policy, const char *buf, size_t count)
> +{
> + return cppc_cpufreq_sysfs_store_u64(policy->cpu, cppc_set_perf_limited, buf, count);
> +}
> +
> cpufreq_freq_attr_ro(freqdomain_cpus);
> cpufreq_freq_attr_rw(auto_select);
> cpufreq_freq_attr_rw(auto_act_window);
> cpufreq_freq_attr_rw(energy_performance_preference_val);
> cpufreq_freq_attr_rw(min_perf);
> cpufreq_freq_attr_rw(max_perf);
> +cpufreq_freq_attr_rw(perf_limited);
>
> static struct freq_attr *cppc_cpufreq_attr[] = {
> &freqdomain_cpus,
> @@ -1057,6 +1068,7 @@ static struct freq_attr *cppc_cpufreq_attr[] = {
> &energy_performance_preference_val,
> &min_perf,
> &max_perf,
> + &perf_limited,
> NULL,
> };
>
> diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> index be7de1222eee..8baff46f2ac7 100644
> --- a/include/acpi/cppc_acpi.h
> +++ b/include/acpi/cppc_acpi.h
> @@ -177,6 +177,8 @@ extern int cppc_get_min_perf(int cpu, u64 *min_perf);
> extern int cppc_set_min_perf(int cpu, u64 min_perf);
> extern int cppc_get_max_perf(int cpu, u64 *max_perf);
> extern int cppc_set_max_perf(int cpu, u64 max_perf);
> +extern int cppc_get_perf_limited(int cpu, u64 *perf_limited);
> +extern int cppc_set_perf_limited(int cpu, u64 perf_limited);
> extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf);
> extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator);
> extern int amd_detect_prefcore(bool *detected);
> @@ -285,6 +287,14 @@ static inline int cppc_set_max_perf(int cpu, u64 max_perf)
> {
> return -EOPNOTSUPP;
> }
> +static inline int cppc_get_perf_limited(int cpu, u64 *perf_limited)
> +{
> + return -EOPNOTSUPP;
> +}
> +static inline int cppc_set_perf_limited(int cpu, u64 perf_limited)
> +{
> + return -EOPNOTSUPP;
> +}
> static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
> {
> return -ENODEV;
next prev parent reply other threads:[~2025-11-27 14:54 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-05 11:38 [PATCH v4 0/8] Enhanced autonomous selection and improvements Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 1/8] cpufreq: CPPC: Add generic helpers for sysfs show/store Sumit Gupta
2025-11-10 10:56 ` Viresh Kumar
2025-11-11 11:20 ` Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 2/8] ACPI: CPPC: Add cppc_get_perf() API to read performance controls Sumit Gupta
2025-11-27 14:53 ` Pierre Gondois
2025-11-28 14:01 ` Sumit Gupta
2025-11-28 15:05 ` Pierre Gondois
2025-11-05 11:38 ` [PATCH v4 3/8] ACPI: CPPC: extend APIs to support auto_sel and epp Sumit Gupta
2025-11-12 15:02 ` Ionela Voinescu
2025-11-18 9:17 ` Sumit Gupta
2025-11-27 14:54 ` Pierre Gondois
2025-12-09 18:10 ` Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 4/8] ACPI: CPPC: add APIs and sysfs interface for min/max_perf Sumit Gupta
2025-11-06 10:30 ` kernel test robot
2025-11-07 10:00 ` Sumit Gupta
2025-11-07 20:08 ` Rafael J. Wysocki
2025-11-11 11:06 ` Sumit Gupta
2025-11-13 10:56 ` Ionela Voinescu
2025-11-18 9:34 ` Sumit Gupta
2025-11-27 14:54 ` Pierre Gondois
2025-12-09 16:38 ` Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 5/8] ACPI: CPPC: add APIs and sysfs interface for perf_limited register Sumit Gupta
2025-11-13 11:35 ` Ionela Voinescu
2025-11-18 10:20 ` Sumit Gupta
2025-11-27 14:54 ` Pierre Gondois [this message]
2025-12-09 17:22 ` Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 6/8] cpufreq: CPPC: Add sysfs for min/max_perf and perf_limited Sumit Gupta
2025-11-13 12:41 ` Ionela Voinescu
2025-11-18 10:46 ` Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 7/8] cpufreq: CPPC: update policy min/max when toggling auto_select Sumit Gupta
2025-11-27 14:53 ` Pierre Gondois
2025-11-28 14:08 ` Sumit Gupta
2025-11-05 11:38 ` [PATCH v4 8/8] cpufreq: CPPC: add autonomous mode boot parameter support Sumit Gupta
2025-11-13 15:15 ` Ionela Voinescu
2025-11-26 13:32 ` Sumit Gupta
2025-11-27 14:53 ` Pierre Gondois
2025-11-28 14:29 ` Sumit Gupta
2025-11-28 15:05 ` Pierre Gondois
2025-12-01 14:09 ` Sumit Gupta
2025-11-10 11:00 ` [PATCH v4 0/8] Enhanced autonomous selection and improvements Viresh Kumar
2025-11-18 8:45 ` Jie Zhan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1decddd7-54d7-4e7e-922d-b68b901bf9aa@arm.com \
--to=pierre.gondois@arm.com \
--cc=acpica-devel@lists.linux.dev \
--cc=bbasu@nvidia.com \
--cc=corbet@lwn.net \
--cc=gautham.shenoy@amd.com \
--cc=ionela.voinescu@arm.com \
--cc=jonathanh@nvidia.com \
--cc=ksitaraman@nvidia.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mario.limonciello@amd.com \
--cc=nhartman@nvidia.com \
--cc=perry.yuan@amd.com \
--cc=rafael@kernel.org \
--cc=ray.huang@amd.com \
--cc=rdunlap@infradead.org \
--cc=robert.moore@intel.com \
--cc=sanjayc@nvidia.com \
--cc=sumitg@nvidia.com \
--cc=treding@nvidia.com \
--cc=viresh.kumar@linaro.org \
--cc=vsethi@nvidia.com \
--cc=zhanjie9@hisilicon.com \
--cc=zhenglifeng1@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).