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b=0I59ZkcfOQkBFReN1EGtwhZsXK7v7hZ38wNXH1UEbNtOkObTBPUlESnOClJ7PjbOtK2v5ulwbEoGjjv0G4DSXj+z+YLZP7OjgKibXOIfi/KdWN4ezQ4+0CTfmScwr2i8hpg5TyMkQkQfK4xbeE8zZaTmY7Hnjj+QjVOmO8cGLOI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MW3PR12MB4553.namprd12.prod.outlook.com (2603:10b6:303:2c::19) by DM4PR12MB7503.namprd12.prod.outlook.com (2603:10b6:8:111::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8943.30; Tue, 22 Jul 2025 15:51:57 +0000 Received: from MW3PR12MB4553.namprd12.prod.outlook.com ([fe80::b0ef:2936:fec1:3a87]) by MW3PR12MB4553.namprd12.prod.outlook.com ([fe80::b0ef:2936:fec1:3a87%3]) with mapi id 15.20.8943.028; Tue, 22 Jul 2025 15:51:57 +0000 Message-ID: <1e8b0a20-d12c-4f1b-9fc5-c4dfafb7c1dd@amd.com> Date: Tue, 22 Jul 2025 10:51:52 -0500 User-Agent: Mozilla Thunderbird Reply-To: babu.moger@amd.com Subject: Re: [PATCH v15 22/34] x86/resctrl: Implement resctrl_arch_reset_cntr() and resctrl_arch_cntr_read() To: Reinette Chatre , corbet@lwn.net, tony.luck@intel.com, james.morse@arm.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com Cc: Dave.Martin@arm.com, x86@kernel.org, hpa@zytor.com, akpm@linux-foundation.org, paulmck@kernel.org, rostedt@goodmis.org, Neeraj.Upadhyay@amd.com, david@redhat.com, arnd@arndb.de, fvdl@google.com, seanjc@google.com, jpoimboe@kernel.org, pawan.kumar.gupta@linux.intel.com, xin@zytor.com, manali.shukla@amd.com, tao1.su@linux.intel.com, sohil.mehta@intel.com, kai.huang@intel.com, xiaoyao.li@intel.com, peterz@infradead.org, xin3.li@intel.com, kan.liang@linux.intel.com, mario.limonciello@amd.com, thomas.lendacky@amd.com, perry.yuan@amd.com, gautham.shenoy@amd.com, chang.seok.bae@intel.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, peternewman@google.com, eranian@google.com References: <272dc6d5-eb63-4dde-8201-880acc9a3846@intel.com> Content-Language: en-US From: "Moger, Babu" In-Reply-To: <272dc6d5-eb63-4dde-8201-880acc9a3846@intel.com> Content-Type: text/plain; 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Reading QM_CTR will then return the contents of the specified >> counter ID. The E bit will be set if the counter configuration was invalid, > > Where is "the E bit" defined? QM_CTR MSRS bits Bits Mnemonic Description. 63 E Error on access to counter 62 U Count for this event is currently unavailable 61-CNT_LEN _ Reserved, read as zero CNT_LEN-1:0 CNT Count of monitored resource or event The bit 63 is "E bit" -> RMID_VAL_ERROR the bit 62 is "U bit" -> RMID_VAL_UNAVAIL How about? The RMID_VAL_ERROR bit will be set if the counter configuration was invalid, or if an invalid counter ID was set in the QM_EVTSEL[RMID] field >> or if an invalid counter ID was set in the QM_EVTSEL[RMID] field. >> >> Introduce resctrl_arch_reset_cntr() and resctrl_arch_cntr_read() to read >> event data for a specific counter. > > hmmm ... they cannot both be used to read the event data? > Yes. Corrected it. >> >> Signed-off-by: Babu Moger >> --- > > ... > >> --- >> arch/x86/kernel/cpu/resctrl/internal.h | 6 +++ >> arch/x86/kernel/cpu/resctrl/monitor.c | 70 ++++++++++++++++++++++++++ >> 2 files changed, 76 insertions(+) >> >> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h >> index 6bf6042f11b6..ae4003d44df4 100644 >> --- a/arch/x86/kernel/cpu/resctrl/internal.h >> +++ b/arch/x86/kernel/cpu/resctrl/internal.h >> @@ -40,6 +40,12 @@ struct arch_mbm_state { >> /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ >> #define ABMC_ENABLE_BIT 0 >> >> +/* >> + * Qos Event Identifiers. >> + */ >> +#define ABMC_EXTENDED_EVT_ID BIT(31) >> +#define ABMC_EVT_ID BIT(0) >> + >> /** >> * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share >> * a resource for a control function >> diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c >> index a230d98e9d73..026c2e2d19d3 100644 >> --- a/arch/x86/kernel/cpu/resctrl/monitor.c >> +++ b/arch/x86/kernel/cpu/resctrl/monitor.c >> @@ -259,6 +259,76 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *d, >> return 0; >> } >> >> +static int __cntr_id_read(u32 cntr_id, u64 *val) >> +{ >> + u64 msr_val; >> + >> + /* >> + * QM_EVTSEL Register definition: >> + * ======================================================= >> + * Bits Mnemonic Description >> + * ======================================================= >> + * 63:44 -- Reserved >> + * 43:32 RMID Resource Monitoring Identifier >> + * 31 ExtEvtID Extended Event Identifier >> + * 30:8 -- Reserved >> + * 7:0 EvtID Event Identifier >> + * ======================================================= >> + * The contents of a specific counter can be read by setting the >> + * following fields in QM_EVTSEL.ExtendedEvtID(=1) and >> + * QM_EVTSEL.EvtID = L3CacheABMC (=1) and setting [RMID] to the >> + * desired counter ID. Reading QM_CTR will then return the >> + * contents of the specified counter. The E bit will be set if the >> + * counter configuration was invalid, or if an invalid counter ID >> + * was set in the QM_EVTSEL[RMID] field. > > (same comments as changelog) "The E bit" -> "The RMID_VAL_ERROR bit" > >> + */ >> + wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id); >> + rdmsrl(MSR_IA32_QM_CTR, msr_val); >> + >> + if (msr_val & RMID_VAL_ERROR) >> + return -EIO; >> + if (msr_val & RMID_VAL_UNAVAIL) >> + return -EINVAL; > > One of these must be the "E bit" (unclear which), leaving other undefined? > >> + >> + *val = msr_val; >> + return 0; >> +} >> + >> +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_mon_domain *d, >> + u32 unused, u32 rmid, int cntr_id, >> + enum resctrl_event_id eventid) >> +{ >> + struct rdt_hw_mon_domain *hw_dom = resctrl_to_arch_mon_dom(d); >> + struct arch_mbm_state *am; >> + >> + am = get_arch_mbm_state(hw_dom, rmid, eventid); >> + if (am) { >> + memset(am, 0, sizeof(*am)); >> + >> + /* Record any initial, non-zero count value. */ >> + __cntr_id_read(cntr_id, &am->prev_msr); >> + } >> +} >> + >> +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_mon_domain *d, >> + u32 unused, u32 rmid, int cntr_id, >> + enum resctrl_event_id eventid, >> + u64 *val, void *ignored) >> +{ >> + u64 msr_val; >> + int ret; >> + >> + resctrl_arch_rmid_read_context_check(); > > Is this needed? I see this context check as related to the MPAM cache occupancy > counters that need to be allocated when a counter is read (see comments of > resctrl_arch_rmid_read() in include/linux/resctrl.h). To me this does not seem > relevant to this work since all allocations should already have been done > when the counter was allocated, no? Yes. No required. Removed it. > >> + >> + ret = __cntr_id_read(cntr_id, &msr_val); >> + if (ret) >> + return ret; >> + >> + *val = mbm_corrected_val(r, d, rmid, eventid, msr_val); >> + >> + return 0; >> +} >> + >> /* >> * The power-on reset value of MSR_RMID_SNC_CONFIG is 0x1 >> * which indicates that RMIDs are configured in legacy mode. > > Reinette > > -- Thanks Babu Moger