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AJvYcCWcUbtNVKTbuQ2wuoPDkLTju+MFkvmd0eDUIqgOI8AcH3YKK4iXaxfMe9zVC1tm6b1PCW9cfryaDvs=@vger.kernel.org X-Gm-Message-State: AOJu0YzLb8JTuDm8zSyWJUp5lHFs9bqnY0sTWmcz34dQ4ugaJhRaQbIr nOM2KlThS7Jjh91SwCzZ7Gi3grTDNHXtFPG5Kwj2gWVgoq6rw6M8JZF7ClduWhU= X-Google-Smtp-Source: AGHT+IH1WfaHxfpzCD8if1ibEm5hwL1R88iNPhaHc0ElvUyQHLLOZjwnM6Wwr2C8DTF0zlQaa7BhsQ== X-Received: by 2002:a5d:46d0:0:b0:37d:41cd:ba4e with SMTP id ffacd0b85a97d-381b710dab4mr11534469f8f.48.1730708924645; Mon, 04 Nov 2024 00:28:44 -0800 (PST) Received: from localhost ([2a01:e0a:3c5:5fb1:3924:2486:a349:2c6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c10d40casm12550078f8f.27.2024.11.04.00.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 00:28:43 -0800 (PST) From: Jerome Brunet To: Guenter Roeck Cc: Jean Delvare , Jonathan Corbet , Patrick Rudolph , Naresh Solanki , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Delphine CC Chiu , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org Subject: Re: [PATCH v3 4/6] hwmon: (pmbus/core) clear faults after setting smbalert mask In-Reply-To: (Guenter Roeck's message of "Fri, 1 Nov 2024 08:10:27 -0700") References: <20241024-tps25990-v3-0-b6a6e9d4b506@baylibre.com> <20241024-tps25990-v3-4-b6a6e9d4b506@baylibre.com> Date: Mon, 04 Nov 2024 09:28:42 +0100 Message-ID: <1jo72v5rnp.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri 01 Nov 2024 at 08:10, Guenter Roeck wrote: > On Thu, Oct 24, 2024 at 08:10:38PM +0200, Jerome Brunet wrote: >> pmbus_write_smbalert_mask() ignores the errors if the chip can't set >> smbalert mask the standard way. It is not necessarily a problem for the irq >> support if the chip is otherwise properly setup but it may leave an >> uncleared fault behind. >> >> pmbus_core will pick the fault on the next register_check(). The register >> check will fails regardless of the actual register support by the chip. >> >> This leads to missing attributes or debugfs entries for chips that should >> provide them. >> >> We cannot rely on register_check() as PMBUS_SMBALERT_MASK may be read-only. >> >> Unconditionally clear the page fault after setting PMBUS_SMBALERT_MASK to >> avoid the problem. >> >> Suggested-by: Guenter Roeck >> Fixes: 221819ca4c36 ("hwmon: (pmbus/core) Add interrupt support") >> Signed-off-by: Jerome Brunet >> --- >> drivers/hwmon/pmbus/pmbus_core.c | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c >> index ce697ca03de01c0e5a352f8f6b72671137721868..a0a397d571caa1a6620ef095f9cf63d94e8bda1d 100644 >> --- a/drivers/hwmon/pmbus/pmbus_core.c >> +++ b/drivers/hwmon/pmbus/pmbus_core.c >> @@ -3346,7 +3346,12 @@ static int pmbus_regulator_notify(struct pmbus_data *data, int page, int event) >> >> static int pmbus_write_smbalert_mask(struct i2c_client *client, u8 page, u8 reg, u8 val) >> { >> - return _pmbus_write_word_data(client, page, PMBUS_SMBALERT_MASK, reg | (val << 8)); >> + int ret; >> + >> + ret = _pmbus_write_word_data(client, page, PMBUS_SMBALERT_MASK, reg | (val << 8)); >> + pmbus_clear_fault_page(client, -1); > > Why -1 and not page ? The idea was to clear the fault on the page we are on, basically just skipping setting the page again. I'll change to 'page' > > Guenter -- Jerome