From: Alan Kao <alankao@andestech.com>
To: Atish Patra <atish.patra@wdc.com>
Cc: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <albert@sifive.com>,
"Peter Zijlstra" <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>,
"Namhyung Kim" <namhyung@kernel.org>,
Alex Solomatnikov <sols@sifive.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Nick Hu <nickhu@andestech.com>,
Greentime Hu <greentime@andestech.com>
Subject: Re: [PATCH v4 1/2] perf: riscv: preliminary RISC-V support
Date: Fri, 20 Apr 2018 07:24:18 +0800 [thread overview]
Message-ID: <20180419232418.GA3902@andestech.com> (raw)
In-Reply-To: <c057c7d1-421f-f4eb-3f03-2abda16d876a@wdc.com>
On Thu, Apr 19, 2018 at 12:46:24PM -0700, Atish Patra wrote:
> On 4/17/18 7:13 PM, Alan Kao wrote:
> >This patch provide a basic PMU, riscv_base_pmu, which supports two
> >general hardware event, instructions and cycles. Furthermore, this
> >PMU serves as a reference implementation to ease the portings in
> >the future.
> >
> >riscv_base_pmu should be able to run on any RISC-V machine that
> >conforms to the Priv-Spec. Note that the latest qemu model hasn't
> >fully support a proper behavior of Priv-Spec 1.10 yet, but work
> >around should be easy with very small fixes. Please check
> >https://github.com/riscv/riscv-qemu/pull/115 for future updates.
> >
> >Cc: Nick Hu <nickhu@andestech.com>
> >Cc: Greentime Hu <greentime@andestech.com>
> >Signed-off-by: Alan Kao <alankao@andestech.com>
> >---
> > arch/riscv/Kconfig | 13 +
> > arch/riscv/include/asm/perf_event.h | 79 ++++-
> > arch/riscv/kernel/Makefile | 1 +
> > arch/riscv/kernel/perf_event.c | 482 ++++++++++++++++++++++++++++
> > 4 files changed, 571 insertions(+), 4 deletions(-)
> > create mode 100644 arch/riscv/kernel/perf_event.c
> >
> >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >index c22ebe08e902..90d9c8e50377 100644
> >--- a/arch/riscv/Kconfig
> >+++ b/arch/riscv/Kconfig
> Some check patch errors.
>
> ERROR: spaces required around that '>=' (ctx:WxV)
> #517: FILE: arch/riscv/kernel/perf_event.c:356:
> + if (riscv_pmu->irq >=0 && riscv_pmu->handle_irq) {
> ^
>
> ERROR: spaces required around that '>=' (ctx:WxV)
> #529: FILE: arch/riscv/kernel/perf_event.c:368:
> + if (riscv_pmu->irq >=0) {
> ^
>
> WARNING: braces {} are not necessary for single statement blocks
> #529: FILE: arch/riscv/kernel/perf_event.c:368:
> + if (riscv_pmu->irq >=0) {
> + free_irq(riscv_pmu->irq, NULL);
> + }
>
> WARNING: DT compatible string "riscv,base-pmu" appears un-documented --
> check ./Documentation/devicetree/bindings/
> #626: FILE: arch/riscv/kernel/perf_event.c:465:
> + {.compatible = "riscv,base-pmu", .data = &riscv_base_pmu},
>
> ERROR: trailing whitespace
> #634: FILE: arch/riscv/kernel/perf_event.c:473:
> +^I$
>
> ERROR: do not use assignment in if condition
> #635: FILE: arch/riscv/kernel/perf_event.c:474:
> + if (node && (of_id = of_match_node(riscv_pmu_of_ids, node)))
>
> total: 4 errors, 3 warnings, 595 lines checked
>
>
> Regards,
> Atish
Thanks for pointing this out. I happened to develop this patchset on a machine
without the post-commit settings. A new version is ready.
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next prev parent reply other threads:[~2018-04-19 23:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-18 2:12 [PATCH v4 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V Alan Kao
2018-04-18 2:12 ` [PATCH v4 1/2] perf: riscv: preliminary RISC-V support Alan Kao
2018-04-19 19:46 ` Atish Patra
2018-04-19 23:24 ` Alan Kao [this message]
2018-04-18 2:12 ` [PATCH v4 2/2] perf: riscv: Add Document for Future Porting Guide Alan Kao
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