From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-6.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id 006647E3A6 for ; Tue, 21 Aug 2018 17:19:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727159AbeHUUjx (ORCPT ); Tue, 21 Aug 2018 16:39:53 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:39720 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726715AbeHUUjx (ORCPT ); Tue, 21 Aug 2018 16:39:53 -0400 From: Paul Cercueil To: Thomas Gleixner , Daniel Lezcano , Rob Herring , Thierry Reding , Mark Rutland , Ralf Baechle , Paul Burton , Jonathan Corbet Cc: od@zcrc.me, Mathieu Malaterre , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-mips@linux-mips.org, linux-doc@vger.kernel.org, linux-clk@vger.kernel.org, Paul Cercueil Subject: [PATCH v7 22/24] MIPS: CI20: Reduce system timer and clocksource to 3 MHz Date: Tue, 21 Aug 2018 19:18:46 +0200 Message-Id: <20180821171846.23050-1-paul@crapouillou.net> In-Reply-To: <20180821171635.22740-1-paul@crapouillou.net> References: <20180821171635.22740-1-paul@crapouillou.net> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1534871930; bh=6VZK2eVXiXpHeoFyayU1uTFkj/6anMKLeptcOJ9wiM8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ndOeMtVu9j3bSqMKi2MtlpqTZM+W4hCbNxJ1RY/8ViTbYe4WGWWcPojACW9qJ479ZeIg8EuslBGFXeLxrwDWsdmph/qmISuC33VibCdfAVaqV6SJ5mgVzGAuhtMgRtV0pkiMZEbE5g9wHCFc6lbmqCRn/NCaAEM8qXKzmSBPe84= Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org The default clock (48 MHz) is too fast for the system timer, which fails to report time accurately. Signed-off-by: Paul Cercueil --- Notes: v5: New patch v6: Set also the rate for the clocksource channel's clock v7: No change arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 50cff3cbcc6d..f64d32443097 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -238,3 +238,9 @@ bias-disable; }; }; + +&tcu { + /* 3 MHz for the system timer and clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; + assigned-clock-rates = <3000000>, <3000000>; +}; -- 2.11.0